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1. 发明授权

US06191647B1 Low noise integrated circuit device for reducing a noise on LSI power supply nets to supply electric charges required to operate IC 有权
标题翻译：低噪声集成电路器件，用于降低LSI电源网络上的噪声，以提供操作IC所需的电荷
公开(公告)号：US06191647B1
公开(公告)日：2001-02-20
申请号：US09220372
申请日：1998-12-24
申请人： Katsuya Tanaka , Masayoshi Yagyu , Tatsuya Saito , Tetsuya Uemura , Tomohisa Iwanaga , Hiroki Yamashita , Takeshi Kato
发明人： Katsuya Tanaka , Masayoshi Yagyu , Tatsuya Saito , Tetsuya Uemura , Tomohisa Iwanaga , Hiroki Yamashita , Takeshi Kato
IPC分类号： H03K500
CPC分类号： H03K19/00346
摘要： A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.
摘要翻译：需要具有巨大面积的电容器来减小集成电路的LSI电源网（-DELTAVDD）上的噪声，因为旁路电容器只能使用一部分累积的电荷。基于降低放电高电压的电容器的噪声降低电路，对LSI电源网（-DELTAVDD）的噪声产生相反极性（+ DELTAVDD）的噪声来抑制LSI电源网的噪声。即使使用容量小的冷凝器，也能够获得与大容量的旁路电容器相当的噪声降低效果。

2. 发明授权

US06330703B1 Method and circuit for determining the power consumption requirements for a semiconductor logic circuit and designing the circuit accordingly 失效
标题翻译：用于确定半导体逻辑电路的功耗要求并相应地设计电路的方法和电路
公开(公告)号：US06330703B1
公开(公告)日：2001-12-11
申请号：US09041121
申请日：1998-03-12
申请人： Tatsuya Saito , Masayoshi Yagyu , Hiroki Yamashita , Tsuneyo Chiba , Masakazu Yamamoto
发明人： Tatsuya Saito , Masayoshi Yagyu , Hiroki Yamashita , Tsuneyo Chiba , Masakazu Yamamoto
IPC分类号： G06F1750
CPC分类号： G01R31/3004 , G06F2217/78
摘要： A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal. Through this operation test, operational failure is reduced and the quality of semiconductor chip production is guaranteed, because it is possible to predict accurately the power consumption when designing the logic circuit due to the relationship between the rate of operation and the power consumption.
摘要翻译：逻辑电路通过考虑操作速率的变化来确定半导体集成器件的功耗。控制信号（TEST）被施加到组合电路组中具有多个输入端口A和B的触发器电路组的触发器电路的每个控制信号输入端口（Tin）和逻辑门电路。如果控制信号（TEST）低，触发器电路和逻辑门电路均正常工作。但是，如果控制信号（TEST）为高，则进行功耗测试。不管施加到触发器电路的输入端口D1和D2的输入信号的值如何，触发器电路被控制为具有在时钟Q1与Q2的端口Q1和Q2的高电平和低电平的重复输出信号信号。通过这种操作测试，可以降低运行故障，保证半导体芯片生产的质量，因为由于操作速率和功耗之间的关系，可以准确地预测设计逻辑电路时的功耗。

3. 发明申请

US20050174190A1 Connection structure of high frequency lines and optical transmission module using the connection structure 审中-公开
标题翻译：高频线连接结构和光传输模块采用连接结构
公开(公告)号：US20050174190A1
公开(公告)日：2005-08-11
申请号：US10628234
申请日：2003-07-29
申请人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
发明人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
IPC分类号： H01P5/08
CPC分类号： H01P5/08
摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
摘要翻译：应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。第一传输线的端面基本上被连接到接地导体的导体层覆盖。连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。

4. 发明授权

US07277643B2 Clock extracting fabric in a communication device 失效
标题翻译：在通信设备中的时钟提取结构
公开(公告)号：US07277643B2
公开(公告)日：2007-10-02
申请号：US10629755
申请日：2003-07-30
申请人： Takashige Baba , Tatsuya Saito , Masayoshi Yagyu , Shigeo Oomae
发明人： Takashige Baba , Tatsuya Saito , Masayoshi Yagyu , Shigeo Oomae
IPC分类号： H04B10/00 , H04L27/00 , H04L12/50 , H04J3/06
CPC分类号： H04L25/14 , H04L7/033
摘要： A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals. The selection made in the selection circuit is switched on the basis of the output of a clock signal monitoring circuit that detects the occurrence of abnormalities in the frequency of the extracted clock signal. Thus, the extraction of clock can be continued using other bits in the event of an abnormality in the bit from which the clock is being extracted.
摘要翻译：一种时钟再现系统的信号通信装置，其中从每个并行数据信号中提取时钟信号，以对每个数据信号进行重新排序。该装置包括一个参考时钟信号产生电路，它包括一个时钟提取电路，用于从接收的数据信号的多个比特中提取一个时钟信号;以及时钟信号选择电路，用于选择所提取的时钟信号之一。或者，参考时钟信号发生电路可以包括用于选择多个接收数据信号中的一个的数据信号选择电路和用于从所选位提取时钟信号的时钟提取电路。基于所得到的参考时钟信号，获得相位调整的时钟信号，以对接收到的数据信号的每一位进行重新编码。在选择电路中进行的选择是基于检测提取的时钟信号的频率异常的发生的时钟信号监视电路的输出而被切换的。因此，在提取时钟的位的异常的情况下，可以使用其他位继续提取时钟。

5. 发明申请

US20060082422A1 Connection structure of high frequency lines and optical transmission module using the connection structure 审中-公开
标题翻译：高频线连接结构和光传输模块采用连接结构
公开(公告)号：US20060082422A1
公开(公告)日：2006-04-20
申请号：US11240455
申请日：2005-10-03
申请人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
发明人： Masayoshi Yagyu , Tatsuya Saito , Shigeo Oomae , Mitsuo Akashi
IPC分类号： H03H7/38
CPC分类号： H01P5/08
摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.
摘要翻译：应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。第一传输线的端面基本上被连接到接地导体的导体层覆盖。连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。

6. 发明授权

US5184027A Clock signal supply system 失效
标题翻译：时钟信号供电系统
公开(公告)号：US5184027A
公开(公告)日：1993-02-02
申请号：US688696
申请日：1991-04-22
申请人： Noboru Masuda , Ryotaro Kamikawai , Masayoshi Yagyu , Masakazu Yamamoto , Hiroyuki Itoh , Tatsuya Saito
发明人： Noboru Masuda , Ryotaro Kamikawai , Masayoshi Yagyu , Masakazu Yamamoto , Hiroyuki Itoh , Tatsuya Saito
IPC分类号： C04B35/45 , G06F1/10 , H01L39/12 , H01L39/24
CPC分类号： C04B35/4504 , G06F1/10 , H01L39/126 , H01L39/2419
摘要： A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.
摘要翻译：时钟信号供应系统提供时钟信号的自动精确相位调整。该系统包括产生时钟信号的振荡器和产生相对于由振荡器产生的时钟信号具有预定关系的参考信号的参考发生器。在要接收时钟信号的每个位置，提供调整电路以调整所接收的时钟信号的相位。这种调整电路可以包括可变延迟电路，其接收时钟信号并且产生由具有变化的延迟的时钟信号构成的输出到连接电路的其余部分。此外，可变延迟的输出被反馈到相位差检测电路。参考信号是相位差检测电路的第二输入。该相位差检测电路比较参考信号和可变延迟电路的输出的差异，并将该控制信号产生到可变延迟电路，该可变延迟电路将进一步调节所接收的时钟信号的相位。该调整是在要接收时钟信号的每个位置处执行的，从而提供对时钟信号的相位的自动调整。

7. 发明授权

US08445832B2 Optical communication device 有权
标题翻译：光通信设备
公开(公告)号：US08445832B2
公开(公告)日：2013-05-21
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/08 , H01J43/00 , H01J40/14 , G01R19/00
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

8. 发明授权

US08005130B2 Transmitter and receiver using forward clock overlaying link information 有权
标题翻译：发射机和接收机使用正向时钟叠加链路信息
公开(公告)号：US08005130B2
公开(公告)日：2011-08-23
申请号：US11826300
申请日：2007-07-13
申请人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
发明人： Hidehiro Toyoda , Tatsuya Saito , Hiroki Yamashita , Norio Chujo
IPC分类号： H04B1/38
CPC分类号： H04L7/0337
摘要： A transmitting and receiving technique in which a load on data signal lines is reduced while maintaining a communication quality, thereby making it possible to improve the throughput of data channels. In a transceiver, a transmitter side has an encoder circuit that transmits a bit sequence obtained by encoding link information to a clock signal line, and a receiver side has a clock and data recovery circuit 17 that extracts a clock component from a signal received from the clock signal line, a decoder circuit 19 that decodes the extracted signal to reproduce the link information, and a bit deskew circuit 21 that adjusts a skew that is lower than one bit on the basis of a clock component.
摘要翻译：一种在保持通信质量的同时减少数据信号线上的负载的发送和接收技术，从而可以提高数据信道的吞吐量。在收发机中，发射机侧具有将通过对链路信息进行编码而获得的比特序列发送到时钟信号线的编码器电路，并且接收机侧具有时钟和数据恢复电路17，时钟和数据恢复电路17从从时钟信号线，对所提取的信号进行解码以再现链接信息的解码器电路19以及基于时钟分量来调整低于1比特的歪斜的位歪斜电路21。

9. 发明授权

US07714644B2 Amplifier circuit 失效
标题翻译：放大器电路
公开(公告)号：US07714644B2
公开(公告)日：2010-05-11
申请号：US12166666
申请日：2008-07-02
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F1/26 , H03F1/34 , H03F3/45085 , H03F3/45183 , H03F3/45968 , H03F2200/372 , H03F2200/375 , H03F2203/45534
摘要： An amplifier circuit block and a compensation circuit block are provided. The amplifier circuit block includes an analog adder for subtracting an output signal of the compensation circuit block from an input signal and an amplifier circuit operating in a wide band. The compensation circuit block includes an amplifier circuit with a low offset voltage and a low noise in a low frequency region, an analog adder block for subtracting an output signal of the amplifier circuit from an output signal of the amplifier circuit and generating a differential signal thereof, and a feedback circuit block for negatively feeding back the differential signal to the analog adder. The amplifier circuit block can reduce the offset voltage and the low-band noise by the negative feedback of the differential signal, and at the same time, the operation band of the entire amplifier circuit can be decided by the characteristic of the amplifier circuit.
摘要翻译：提供放大器电路块和补偿电路块。放大器电路块包括用于从输入信号中减去补偿电路块的输出信号的模拟加法器和在宽带中工作的放大器电路。补偿电路块包括在低频区域具有低失调电压和低噪声的放大器电路，用于从放大器电路的输出信号中减去放大器电路的输出信号并产生其差分信号的模拟加法器块以及用于将差分信号负反馈给模拟加法器的反馈电路块。放大器电路块可以通过差分信号的负反馈来减小偏移电压和低带噪声，同时整个放大器电路的工作频带可以由放大器电路的特性决定。

10. 发明申请

US20110316632A1 OPTICAL COMMUNICATION DEVICE 有权
标题翻译：光通信设备
公开(公告)号：US20110316632A1
公开(公告)日：2011-12-29
申请号：US13201212
申请日：2009-03-05
申请人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
发明人： Takashi Takemoto , Hiroki Yamashita , Tatsuya Saito
IPC分类号： H03F3/16 , H03F1/22 , H03G3/20
CPC分类号： H03F3/087 , H03F1/223 , H03F1/34 , H03F3/082 , H03F3/3022 , H03F3/505 , H03F2200/453 , H04B10/6933
摘要： An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
摘要翻译：提供可以高速运转的光通信装置。例如，光通信装置包括：前置放大器电路PREAMP1，放大来自光电二极管PD的电流信号Iin，将放大后的信号变换为电压信号; 以及控制PREAMP1的操作的操作点控制器电路VTCTL1。 PREAMP1包括由反馈电阻Rf1形成的负反馈路径，并且包括：根据工作点控制信号Vcon的电平移位电路LS1电平移位; 以及连接到LS1的后级并且以高增益进行放大操作的放大器电路AMP1。 VTCTL1包括由与AMP1相同的电路和电路参数配置的电路复用电路，并且电连接在输入和输出端之间，并产生Vcon，使得该复制电路的输出直流电平与输入直流电平相匹配的AMP1。

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