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1. 发明申请

US20090047526A1 Method for Manufacturing Semiconductor Wafer 有权
标题翻译：半导体晶片制造方法
公开(公告)号：US20090047526A1
公开(公告)日：2009-02-19
申请号：US11840615
申请日：2007-08-17
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
IPC分类号： H01L21/20 , B32B9/04
CPC分类号： H01L21/76254
摘要： A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layer 12 and a first Si layer 13 in this order on the surface of a silicon wafer 11; (b) forming an SiO2 layer 16 on top of the first Si layer and/or a support wafer 14; (c) forming a layered product 17 by stacking the silicon wafer and the support wafer with the SiO2 layer being placed therebetween; (d) forming a second Si layer 18 by thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.
摘要翻译：本发明提供一种制造半导体晶片的方法，该半导体晶片具有具有足够的拉伸应变和很少的晶体缺陷的应变Si层，同时实现相对简单的分层结构。该方法包括以下步骤：（a）在硅晶片11的表面上依次形成SiGe混晶层12和第一Si层13; （b）在第一Si层和/或支撑晶片14的顶部上形成SiO2层16; （c）通过将硅晶片和支撑晶片叠置在其间的SiO 2层来形成层叠体17; （d）通过使层叠体的硅晶片变薄来形成第二Si层18; （e）植入氢离子和/或稀有气体离子，使得离子浓度在预定区域中峰值; （f）对层叠体进行第一次热处理; 和（g）在第一热处理之后进行第二热处理，从而使SiGe混晶层松弛，并通过第一Si层和第二Si层的一部分扩散Ge。

2. 发明授权

US07767548B2 Method for manufacturing semiconductor wafer including a strained silicon layer 有权
标题翻译：包括应变硅层的半导体晶片的制造方法
公开(公告)号：US07767548B2
公开(公告)日：2010-08-03
申请号：US11840615
申请日：2007-08-17
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layer 12 and a first Si layer 13 in this order on the surface of a silicon wafer 11; (b) forming an SiO2 layer 16 on top of the first Si layer and/or a support wafer 14; (c) forming a layered product 17 by stacking the silicon wafer and the support wafer with the SiO2 layer being placed therebetween; (d) forming a second Si layer 18 by thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.
摘要翻译：本发明提供一种制造半导体晶片的方法，该半导体晶片具有具有足够的拉伸应变和很少的晶体缺陷的应变Si层，同时实现相对简单的分层结构。该方法包括以下步骤：（a）在硅晶片11的表面上依次形成SiGe混晶层12和第一Si层13; （b）在第一Si层和/或支撑晶片14的顶部上形成SiO2层16; （c）通过将硅晶片和支撑晶片叠置在其间的SiO 2层来形成层叠体17; （d）通过使层叠体的硅晶片变薄来形成第二Si层18; （e）植入氢离子和/或稀有气体离子，使得离子浓度在预定区域中峰值; （f）对层叠体进行第一次热处理; 和（g）在第一热处理之后进行第二热处理，从而使SiGe混晶层松弛，并通过第一Si层和第二Si层的一部分扩散Ge。

3. 发明申请

US20090090933A1 METHOD OF PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THE SAME 有权
标题翻译：生产应变Si-SOI衬底和由其制造的应变Si-SOI衬底的方法
公开(公告)号：US20090090933A1
公开(公告)日：2009-04-09
申请号：US11868296
申请日：2007-10-05
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
IPC分类号： H01L29/165 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/76243
摘要： A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
摘要翻译：提供了应变Si-SOI衬底及其制造方法，其中该方法包括以下步骤：在具有Si层13和掩埋氧化膜12的SOI衬底10上生长SiGe混晶层14; 在SiGe混晶层14的表面上形成保护膜15,16; 将光元素离子注入到Si层13和掩埋氧化物膜12之间的界面附近; 在400〜1000℃的温度下进行第一次热处理。在氧化气氛下在不低于1050℃的温度下进行第二次热处理; 在不低于1050℃的温度下在惰性气氛下进行第三次热处理; 去除形成在表面上的Si氧化物膜18; 并形成应变Si层19。

4. 发明授权

US07977221B2 Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same 有权
标题翻译：制造应变Si-SOI衬底及其制造的应变Si-SOI衬底的方法
公开(公告)号：US07977221B2
公开(公告)日：2011-07-12
申请号：US11868296
申请日：2007-10-05
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/1054 , H01L21/76243
摘要： A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
摘要翻译：提供了应变Si-SOI衬底及其制造方法，其中该方法包括以下步骤：在具有Si层13和掩埋氧化膜12的SOI衬底10上生长SiGe混晶层14; 在SiGe混晶层14的表面上形成保护膜15,16; 将光元素离子注入到Si层13和掩埋氧化物膜12之间的界面附近; 在400〜1000℃的温度下进行第一次热处理。在氧化气氛下在不低于1050℃的温度下进行第二次热处理; 在不低于1050℃的温度下在惰性气氛下进行第三次热处理; 去除形成在表面上的Si氧化物膜18; 并形成应变Si层19。

5. 发明申请

US20060214257A1 Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by same 审中-公开
标题翻译：应变硅SOI衬底和应变硅SOI衬底的生产方法
公开(公告)号：US20060214257A1
公开(公告)日：2006-09-28
申请号：US11388538
申请日：2006-03-23
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
IPC分类号： H01L21/00 , H01L29/00
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/324 , H01L21/76251
摘要： A strained Si-SOI substrate is produced by a method comprising: growing a SiGe mixed crystal layer on an SOI substrate having a Si layer of not less than 5 nm in thickness and a buried oxide layer; forming a protective film on the SiGe mixed crystal layer; implanting light element ions into a vicinity of an interface between the silicon layer and the buried oxide layer; a first heat treatment for heat treating the substrate at a temperature of 400 to 1000° C. in an inert gas atmosphere; a second heat treatment for heat treating the substrate at a temperature not lower than 1050° C. in an oxidizing atmosphere containing chlorine; removing an oxide film from the surface of the substrate, and forming a strained silicon layer on the surface of the substrate.
摘要翻译：通过以下方法制造应变Si-SOI衬底，该方法包括：在具有不小于5nm的Si层的SOI衬底上生长SiGe混合晶体层和掩埋氧化物层; 在SiGe混晶层上形成保护膜; 将光元素离子注入硅层和掩埋氧化物层之间的界面附近; 在惰性气体气氛中在400〜1000℃的温度下热处理基板的第一热处理; 在含有氯的氧化气氛中，在不低于1050℃的温度下对基材进行热处理的第二热处理; 从衬底的表面去除氧化膜，并在衬底的表面上形成应变硅层。

6. 发明申请

US20050081958A1 Pasted soi substrate, process for producing the same and semiconductor device 有权
标题翻译：糊状基底，其制造方法和半导体器件
公开(公告)号：US20050081958A1
公开(公告)日：2005-04-21
申请号：US10501522
申请日：2003-10-22
申请人： Naoshi Adachi , Masahiko Nakamae
发明人： Naoshi Adachi , Masahiko Nakamae
IPC分类号： H01L21/02 , H01L21/336 , H01L21/762 , H01L21/764 , H01L27/12 , H01L29/786 , H01L21/30
CPC分类号： H01L21/764 , H01L21/76251 , H01L21/76254
摘要： A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a cavity of higher dimensional precision to be buried therein. A plurality of cavities may be formed simultaneously in a plurality of locations within the plane of the substrate, which allows the thickness of the SOI layer to be set arbitrarily. Accordingly, such a semiconductor device can be fabricated easily in which a MOS type element and a bipolar element are formed on the same chip in a mixed manner.
摘要翻译：在有源层晶片的表面或支撑衬底晶片的接合表面上形成具有不同深度的多个凹部。这些晶片通过绝缘膜彼此接合。这允许将较高尺寸精度的腔埋入其中。可以在衬底的平面内的多个位置中同时形成多个空腔，这允许SOI层的厚度任意设定。因此，可以容易地制造这样的半导体器件，其中在相同的芯片上以混合的方式形成MOS型元件和双极元件。

7. 发明授权

US06372628B1 Insulating film comprising amorphous carbon fluoride, a semiconductor device comprising such an insulating film, and a method for manufacturing the semiconductor device 失效
标题翻译：包含无定形氟化碳的绝缘膜，包括这种绝缘膜的半导体器件及其半导体器件的制造方法
公开(公告)号：US06372628B1
公开(公告)日：2002-04-16
申请号：US09579474
申请日：2000-05-26
申请人： Yoshihisa Matsubara , Ko Noguchi , Shinya Ito , Noriaki Oda , Akira Matsumoto , Takashi Ishigami , Masahiko Nakamae , Tadahiko Horiuchi , Kazuhiko Endo , Toru Tatsumi , Yoshishige Matsumoto
发明人： Yoshihisa Matsubara , Ko Noguchi , Shinya Ito , Noriaki Oda , Akira Matsumoto , Takashi Ishigami , Masahiko Nakamae , Tadahiko Horiuchi , Kazuhiko Endo , Toru Tatsumi , Yoshishige Matsumoto
IPC分类号： H01L214763
CPC分类号： H01L21/02118 , H01L21/02126 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/312 , H01L21/3185 , H01L21/76801 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L23/53223 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
摘要翻译：公开了在布线层和使用这种膜的半导体器件之间使用的低介电常数层间绝缘膜的结构和制造工艺。可以在实际工艺中承受的绝缘膜包括无定形氟化碳膜。在无定形氟化碳膜的两侧设置有类金刚石碳膜和硅过剩层，以插入布线层之间，从而显着提高与布线的接合和与其接触的另一绝缘膜。另外，将硅基绝缘膜设置并平坦化在含有埋设有布线层的无定形氟化碳膜的多层膜上，并且用作用于各向异性蚀刻金刚石状碳膜和无定形氟化碳膜的硬掩模，氧等离子体形成通孔。

8. 发明授权

US4191595A Method of manufacturing PN junctions in a semiconductor region to reach an isolation layer without exposing the semiconductor region surface 失效
标题翻译：在半导体区域中制造PN结以在不暴露半导体区域表面的情况下到达隔离层的方法
公开(公告)号：US4191595A
公开(公告)日：1980-03-04
申请号：US835328
申请日：1977-09-21
申请人： Kunio Aomura , Fujiki Tokuyoshi , Masahiko Nakamae
发明人： Kunio Aomura , Fujiki Tokuyoshi , Masahiko Nakamae
IPC分类号： H01L21/70 , H01L21/033 , H01L21/265 , H01L21/3115 , H01L21/76 , H01L21/762 , H01L29/72 , H01L21/225
CPC分类号： H01L21/76202 , H01L21/033 , H01L21/31155
摘要： In a semiconductor device including at least one active semiconductor region isolated by an oxide layer in a semiconductor substrate having a principal surface, at least two PN junctions, terminating at the oxide layer, are formed in the active region, by introduction of impurities into the active region with the active region surface never exposed during their formation. The junctions may partly reach the principal surface. The impurities may be introduced by ion implantation through a thin oxide film overlying the active region, and through use of other films placed on the oxide film, or by the known melt-through technique. At least one junction may be formed by epitaxial growth of a semiconductor layer of the opposite conductivity type.
摘要翻译：在包括由具有主表面的半导体衬底中的氧化物层隔离的至少一个有源半导体区域的半导体器件中，通过在有源区中形成终止于氧化物层的至少两个PN结，通过将杂质引入到活性区域，其活性区域表面在其形成期间永不暴露。交界部分可能部分到达主面。杂质可以通过离子注入通过覆盖有源区的薄氧化膜，以及通过使用放置在氧化物膜上的其它膜，或通过已知的熔化技术引入。可以通过相反导电类型的半导体层的外延生长来形成至少一个结。

9. 发明授权

US07253082B2 Pasted SOI substrate, process for producing the same and semiconductor device 有权
标题翻译：粘贴的SOI衬底，其制造方法和半导体器件
公开(公告)号：US07253082B2
公开(公告)日：2007-08-07
申请号：US10501522
申请日：2003-10-22
申请人： Naoshi Adachi , Masahiko Nakamae
发明人： Naoshi Adachi , Masahiko Nakamae
IPC分类号： H01L21/30
CPC分类号： H01L21/764 , H01L21/76251 , H01L21/76254
摘要： A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a cavity of higher dimensional precision to be buried therein. A plurality of cavities may be formed simultaneously in a plurality of locations within the plane of the substrate, which allows the thickness of the SOI layer to be set arbitrarily. Accordingly, such a semiconductor device can be fabricated easily in which a MOS type element and a bipolar element are formed on the same chip in a mixed manner.
摘要翻译：在有源层晶片的表面或支撑衬底晶片的接合表面上形成具有不同深度的多个凹部。这些晶片通过绝缘膜彼此接合。这允许将较高尺寸精度的腔埋入其中。可以在衬底的平面内的多个位置中同时形成多个空腔，这允许SOI层的厚度任意设定。因此，可以容易地制造这样的半导体器件，其中在相同的芯片上以混合的方式形成MOS型元件和双极元件。

10. 发明授权

US5296391A Method of manufacturing a bipolar transistor having thin base region 失效
标题翻译：制造具有薄基极区域的双极晶体管的制造方法
公开(公告)号：US5296391A
公开(公告)日：1994-03-22
申请号：US67017
申请日：1993-05-26
申请人： Fumihiko Sato , Masahiko Nakamae , Mitsuhiro Sugiyama , Tsutomu Tashiro
发明人： Fumihiko Sato , Masahiko Nakamae , Mitsuhiro Sugiyama , Tsutomu Tashiro
IPC分类号： H01L21/331 , H01L29/732 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66287 , H01L29/66242 , H01L29/732 , H01L29/7378 , Y10S148/01
摘要： A method of manufacturing a semiconductor device includes a monocrystalline semiconductor layer of one conductivity type with a first insulating film covering the semiconductor layer. An aperture is selectively formed in the first insulating film to expose a part of the semiconductor layer. A first polycrystalline semiconductor film of an opposite conductivity type is formed on the first insulating film and has an overhang portion projecting over the aperture from an edge of the first insulating film defining the aperture. A second polycrystalline semiconductor film and a monocrystalline semiconductor film of the opposite conductivity type are grown simultaneously on a bottom surface of the overhang portion of the first polycrystalline semiconductor film and on the part of the monocrystalline semiconductor layer respectively until monocrystalline semiconductor film is in contact with the second polycrystalline semiconductor film, with a second insulating film selectively formed on the monocrystalline semiconductor film with leaving a part thereof to be exposed.
摘要翻译：半导体器件的制造方法包括具有覆盖半导体层的第一绝缘膜的一种导电型单晶半导体层。在第一绝缘膜中选择性地形成孔径以暴露半导体层的一部分。具有相反导电型的第一多晶半导体膜形成在第一绝缘膜上，并且具有从限定孔的第一绝缘膜的边缘在孔上突出的突出部分。在第一多晶半导体膜的突出部分的底表面和单晶半导体层的一部分上同时生长具有相反导电类型的第二多晶半导体膜和单晶半导体膜，直到单晶半导体膜与所述第二多晶半导体膜具有选择性地形成在所述单晶半导体膜上并使其一部分露出的第二绝缘膜。

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