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1. 发明申请

US20090090933A1 METHOD OF PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THE SAME 有权
标题翻译：生产应变Si-SOI衬底和由其制造的应变Si-SOI衬底的方法
公开(公告)号：US20090090933A1
公开(公告)日：2009-04-09
申请号：US11868296
申请日：2007-10-05
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
IPC分类号： H01L29/165 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/76243
摘要： A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
摘要翻译：提供了应变Si-SOI衬底及其制造方法，其中该方法包括以下步骤：在具有Si层13和掩埋氧化膜12的SOI衬底10上生长SiGe混晶层14; 在SiGe混晶层14的表面上形成保护膜15,16; 将光元素离子注入到Si层13和掩埋氧化物膜12之间的界面附近; 在400〜1000℃的温度下进行第一次热处理。在氧化气氛下在不低于1050℃的温度下进行第二次热处理; 在不低于1050℃的温度下在惰性气氛下进行第三次热处理; 去除形成在表面上的Si氧化物膜18; 并形成应变Si层19。

2. 发明申请

US20090047526A1 Method for Manufacturing Semiconductor Wafer 有权
标题翻译：半导体晶片制造方法
公开(公告)号：US20090047526A1
公开(公告)日：2009-02-19
申请号：US11840615
申请日：2007-08-17
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
IPC分类号： H01L21/20 , B32B9/04
CPC分类号： H01L21/76254
摘要： A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layer 12 and a first Si layer 13 in this order on the surface of a silicon wafer 11; (b) forming an SiO2 layer 16 on top of the first Si layer and/or a support wafer 14; (c) forming a layered product 17 by stacking the silicon wafer and the support wafer with the SiO2 layer being placed therebetween; (d) forming a second Si layer 18 by thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.
摘要翻译：本发明提供一种制造半导体晶片的方法，该半导体晶片具有具有足够的拉伸应变和很少的晶体缺陷的应变Si层，同时实现相对简单的分层结构。该方法包括以下步骤：（a）在硅晶片11的表面上依次形成SiGe混晶层12和第一Si层13; （b）在第一Si层和/或支撑晶片14的顶部上形成SiO2层16; （c）通过将硅晶片和支撑晶片叠置在其间的SiO 2层来形成层叠体17; （d）通过使层叠体的硅晶片变薄来形成第二Si层18; （e）植入氢离子和/或稀有气体离子，使得离子浓度在预定区域中峰值; （f）对层叠体进行第一次热处理; 和（g）在第一热处理之后进行第二热处理，从而使SiGe混晶层松弛，并通过第一Si层和第二Si层的一部分扩散Ge。

3. 发明授权

US07977221B2 Method for producing strained Si-SOI substrate and strained Si-SOI substrate produced by the same 有权
标题翻译：制造应变Si-SOI衬底及其制造的应变Si-SOI衬底的方法
公开(公告)号：US07977221B2
公开(公告)日：2011-07-12
申请号：US11868296
申请日：2007-10-05
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/1054 , H01L21/76243
摘要： A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
摘要翻译：提供了应变Si-SOI衬底及其制造方法，其中该方法包括以下步骤：在具有Si层13和掩埋氧化膜12的SOI衬底10上生长SiGe混晶层14; 在SiGe混晶层14的表面上形成保护膜15,16; 将光元素离子注入到Si层13和掩埋氧化物膜12之间的界面附近; 在400〜1000℃的温度下进行第一次热处理。在氧化气氛下在不低于1050℃的温度下进行第二次热处理; 在不低于1050℃的温度下在惰性气氛下进行第三次热处理; 去除形成在表面上的Si氧化物膜18; 并形成应变Si层19。

4. 发明申请

US20060214257A1 Production method of strained silicon-SOI substrate and strained silicon-SOI substrate produced by same 审中-公开
标题翻译：应变硅SOI衬底和应变硅SOI衬底的生产方法
公开(公告)号：US20060214257A1
公开(公告)日：2006-09-28
申请号：US11388538
申请日：2006-03-23
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao
IPC分类号： H01L21/00 , H01L29/00
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/324 , H01L21/76251
摘要： A strained Si-SOI substrate is produced by a method comprising: growing a SiGe mixed crystal layer on an SOI substrate having a Si layer of not less than 5 nm in thickness and a buried oxide layer; forming a protective film on the SiGe mixed crystal layer; implanting light element ions into a vicinity of an interface between the silicon layer and the buried oxide layer; a first heat treatment for heat treating the substrate at a temperature of 400 to 1000° C. in an inert gas atmosphere; a second heat treatment for heat treating the substrate at a temperature not lower than 1050° C. in an oxidizing atmosphere containing chlorine; removing an oxide film from the surface of the substrate, and forming a strained silicon layer on the surface of the substrate.
摘要翻译：通过以下方法制造应变Si-SOI衬底，该方法包括：在具有不小于5nm的Si层的SOI衬底上生长SiGe混合晶体层和掩埋氧化物层; 在SiGe混晶层上形成保护膜; 将光元素离子注入硅层和掩埋氧化物层之间的界面附近; 在惰性气体气氛中在400〜1000℃的温度下热处理基板的第一热处理; 在含有氯的氧化气氛中，在不低于1050℃的温度下对基材进行热处理的第二热处理; 从衬底的表面去除氧化膜，并在衬底的表面上形成应变硅层。

5. 发明授权

US07767548B2 Method for manufacturing semiconductor wafer including a strained silicon layer 有权
标题翻译：包括应变硅层的半导体晶片的制造方法
公开(公告)号：US07767548B2
公开(公告)日：2010-08-03
申请号：US11840615
申请日：2007-08-17
申请人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
发明人： Masaharu Ninomiya , Koji Matsumoto , Masahiko Nakamae , Masanobu Miyao , Taizoh Sadoh
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided. The method includes the steps of: (a) forming an SiGe mixed crystal layer 12 and a first Si layer 13 in this order on the surface of a silicon wafer 11; (b) forming an SiO2 layer 16 on top of the first Si layer and/or a support wafer 14; (c) forming a layered product 17 by stacking the silicon wafer and the support wafer with the SiO2 layer being placed therebetween; (d) forming a second Si layer 18 by thinning the silicon wafer of the layered product; (e) implanting hydrogen ion and/or rare gas ion, such that ionic concentration peaks in a predetermined area; (f) subjecting the layered product to a first heat treatment; and (g) carrying out a second heat treatment following the first heat treatment, thereby relaxing the SiGe mixed crystal layer and diffusing Ge through portions of the first Si layer and the second Si layer.
摘要翻译：本发明提供一种制造半导体晶片的方法，该半导体晶片具有具有足够的拉伸应变和很少的晶体缺陷的应变Si层，同时实现相对简单的分层结构。该方法包括以下步骤：（a）在硅晶片11的表面上依次形成SiGe混晶层12和第一Si层13; （b）在第一Si层和/或支撑晶片14的顶部上形成SiO2层16; （c）通过将硅晶片和支撑晶片叠置在其间的SiO 2层来形成层叠体17; （d）通过使层叠体的硅晶片变薄来形成第二Si层18; （e）植入氢离子和/或稀有气体离子，使得离子浓度在预定区域中峰值; （f）对层叠体进行第一次热处理; 和（g）在第一热处理之后进行第二热处理，从而使SiGe混晶层松弛，并通过第一Si层和第二Si层的一部分扩散Ge。

6. 发明授权

US07579229B2 Semiconductor device and semiconductor substrate 失效
标题翻译：半导体器件和半导体衬底
公开(公告)号：US07579229B2
公开(公告)日：2009-08-25
申请号：US12010123
申请日：2008-01-22
申请人： Nobuyuki Sugii , Kiyokazu Nakagawa , Shinya Yamaguchi , Masanobu Miyao
发明人： Nobuyuki Sugii , Kiyokazu Nakagawa , Shinya Yamaguchi , Masanobu Miyao
IPC分类号： H01L21/762
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/7782 , H01L29/7848
摘要： In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
摘要翻译：为了提供一种具有低功耗和高速的场效晶体管的半导体器件，其通过使用Si和诸如与Si相同的组的诸如Ge，C等元素的组合，施加应变通过将半导体层2施加到其中形成有场效应晶体管的沟道的沟道形成层I的应变，使得沟道中的载流子的迁移率大于沟道形成层的材料中的载流子的迁移率，无限制

7. 发明授权

US06888162B2 Electronic apparatus having polycrystalline semiconductor thin film structure 失效
标题翻译：具有多晶半导体薄膜结构的电子设备
公开(公告)号：US06888162B2
公开(公告)日：2005-05-03
申请号：US10354121
申请日：2003-01-30
申请人： Shinya Yamaguchi , Masanobu Miyao , Kiyokazu Nakagawa , Nobuyuki Sugii
发明人： Shinya Yamaguchi , Masanobu Miyao , Kiyokazu Nakagawa , Nobuyuki Sugii
IPC分类号： G06F15/78 , G02F1/136 , G02F1/1368 , H01L21/20 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/04 , H01L29/786
CPC分类号： H01L21/02686 , H01L21/2026 , H01L27/1281 , H01L27/1285 , H01L27/1296 , H01L29/04 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/78654 , H01L29/78675 , H01L29/78684
摘要： An electronic apparatus employs a polycrystalline semiconductor thin film structure formed of an insulating substrate and a plurality of polycrystalline layers laminated on the insulating substrate. A plurality of transistors are formed at the surface of the polycrystalline semiconductor thin film structure, each transistor being formed in a region of one of a plurality of crystal grains disseminated on the surface of the polycrystalline layers. A number of crystal grains in each of the polycrystalline layers is gradually reduced from a lower layer to an upper layer.
摘要翻译：电子设备采用由绝缘基板和层叠在绝缘基板上的多个多晶层形成的多晶半导体薄膜结构。在多晶半导体薄膜结构的表面形成多个晶体管，每个晶体管形成在多晶层的表面上散布的多个晶粒中的一个晶体管的区域中。各个多晶层中的多个晶粒从下层逐渐减小到上层。

8. 发明授权

US5241197A Transistor provided with strained germanium layer 失效
标题翻译：晶体管配有应变锗层
公开(公告)号：US5241197A
公开(公告)日：1993-08-31
申请号：US759772
申请日：1991-09-13
申请人： Eiichi Murakami , Kiyokazu Nakagawa , Takashi Ohshima , Hiroyuki Eto , Masanobu Miyao
发明人： Eiichi Murakami , Kiyokazu Nakagawa , Takashi Ohshima , Hiroyuki Eto , Masanobu Miyao
IPC分类号： H01L27/085 , H01L29/165 , H01L29/737 , H01L29/778 , H01L29/80
CPC分类号： H01L29/7378 , H01L27/085 , H01L29/165 , H01L29/7373 , H01L29/7782 , H01L29/802
摘要： A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.
摘要翻译：可以通过利用应变锗层中的载流子迁移率大的事实来形成具有高载流子迁移率且适于高速操作的晶体管。在锗层下方设置应变控制层，以在锗层上施加压缩应变，并且使用预定范围内的应变控制层的组成以确定地产生压缩应变。

9. 发明授权

US06545294B1 ELECTRONIC APPARATUS HAVING SEMICONDUCTOR DEVICE INCLUDING PLURALITY OF TRANSISTORS FORMED ON A POLYCRYSTALLINE LAYERED STRUCTURE IN WHICH THE NUMBER OF CRYSTAL GRAINS IN EACH POLYCRYSTALLINE LAYER IS GRADUALLY REDUCED FROM LOWER TO UPPER LAYER 失效
标题翻译：具有半导体器件的电子设备，包括在多晶层结构中形成的晶体管的多样性，其中每个多晶层中的晶粒数量从较低层次降低到上层
公开(公告)号：US06545294B1
公开(公告)日：2003-04-08
申请号：US09571937
申请日：2000-05-16
申请人： Shinya Yamaguchi , Masanobu Miyao , Kiyokazu Nakagawa , Nobuyuki Sugii
发明人： Shinya Yamaguchi , Masanobu Miyao , Kiyokazu Nakagawa , Nobuyuki Sugii
IPC分类号： H01L2904
CPC分类号： H01L21/02686 , H01L21/2026 , H01L27/1281 , H01L27/1285 , H01L27/1296 , H01L29/04 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/78654 , H01L29/78675 , H01L29/78684
摘要： The present invention provides an apparatus having a semiconductor device including a plurality of transistors formed on respective single crystal silicon regions of enlarged grain size. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tips of projections are composed of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating the above process a plurality of times, and by gradually enlarging the pitch, span, size and height of projections, the size of the crystal grains of silicon at the surface may be enlarged to the extent required. Thereby, silicon crystal grains of large grain size with the crystal orientation aligned may be formed at controllable positions.
摘要翻译：本发明提供一种具有半导体器件的装置，该半导体器件包括形成在增大晶粒尺寸的各个单晶硅区域上的多个晶体管。在多晶硅层上，通过使用各向异性蚀刻和光掩模形成规则间隔的突起。突起的尖端由通过各向异性蚀刻选择性留下的特定晶体取向的单晶硅组成，其是沉积在其上的非晶硅的核的候选者。通过多次迭代上述处理，并且通过逐渐扩大突起的间距，跨度，尺寸和高度，可以将表面处的硅晶粒的尺寸扩大到所需的程度。由此，可以在可控位置形成具有晶体取向取向的大晶粒尺寸的硅晶粒。

10. 发明授权

US5237528A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5237528A
公开(公告)日：1993-08-17
申请号：US822325
申请日：1992-01-17
申请人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
发明人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
IPC分类号： G11C11/404 , H01L27/108 , H01L29/94
CPC分类号： G11C11/404 , H01L27/10829 , H01L27/10841 , H01L29/945
摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
摘要翻译：半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接到绝缘栅场效应晶体管的源极或漏极。提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层底物。

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