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1. 发明申请

US20120211862A1 SOI SUBSTRATE AND METHOD FOR MANUFACTURING SOI SUBSTRATE 审中-公开
标题翻译： SOI衬底和制造SOI衬底的方法
公开(公告)号：US20120211862A1
公开(公告)日：2012-08-23
申请号：US13372541
申请日：2012-02-14
申请人： Masaharu NAGAI , Hideto OHNUMA , Kosei NEI
发明人： Masaharu NAGAI , Hideto OHNUMA , Kosei NEI
IPC分类号： H01L29/06 , H01L21/762 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/3065 , H01L21/76254
摘要： The method for manufacturing an SOI substrate includes the following steps: forming an insulating film on a semiconductor substrate; exposing the semiconductor substrate to accelerated ions so that an embrittlement region is formed in the semiconductor substrate; bonding the semiconductor substrate to a base substrate with the insulating film interposed therebetween; separating the semiconductor substrate along the embrittlement region so that a semiconductor film is provided over the base substrate with the insulating film interposed therebetween; and forming a mask over the semiconductor film to etch part of the semiconductor film and part of the insulating film so that the periphery of the semiconductor film is on the inner side than the periphery of the insulating film.
摘要翻译： SOI衬底的制造方法包括以下步骤：在半导体衬底上形成绝缘膜; 将半导体衬底暴露于加速离子，使得在半导体衬底中形成脆化区; 将所述半导体基板与绝缘膜接合在基底基板上; 沿着所述脆化区域分离所述半导体衬底，使得半导体膜设置在所述基底衬底上，所述绝缘膜置于所述基底衬底之间; 以及在所述半导体膜上形成掩模以蚀刻所述半导体膜的一部分和所述绝缘膜的一部分，使得所述半导体膜的周边位于比所述绝缘膜的周边的内侧。

2. 发明申请

US20110039395A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20110039395A1
公开(公告)日：2011-02-17
申请号：US12910320
申请日：2010-10-22
申请人： Hideto OHNUMA , Kenichiro MAKINO , Yoichi IIKUBO , Masaharu NAGAI , Aiko SHIGA
发明人： Hideto OHNUMA , Kenichiro MAKINO , Yoichi IIKUBO , Masaharu NAGAI , Aiko SHIGA
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/66772 , H01L29/78621
摘要： To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.
摘要翻译：即使使用含有氮的绝缘膜作为接合层，为了提高接合强度并提高SOI基板的接合半导体基板和基板的可靠性，在半导体基板侧设置氧化膜，氮在基底基板侧设置含氧层，并且形成在半导体基板上的氧化膜和形成在基底基板上的含氮层彼此结合。此外，在将形成在半导体衬底上的氧化膜和形成在基底衬底上的含氮层彼此粘合之前，对氧化物膜和含氮层中的至少一种进行等离子体处理。可以在施加偏置电压的状态下进行等离子体处理。

3. 发明申请

US20090325363A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20090325363A1
公开(公告)日：2009-12-31
申请号：US12489594
申请日：2009-06-23
申请人： Hideto OHNUMA , Kenichiro MAKINO , Yoichi IIKUBO , Masaharu NAGAI , Aiko SHIGA
发明人： Hideto OHNUMA , Kenichiro MAKINO , Yoichi IIKUBO , Masaharu NAGAI , Aiko SHIGA
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/76254 , H01L29/66772 , H01L29/78621
摘要： To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.
摘要翻译：即使使用含有氮的绝缘膜作为接合层，为了提高接合强度并提高SOI基板的接合半导体基板和基板的可靠性，在半导体基板侧设置氧化膜，氮在基底基板侧设置含氧层，并且形成在半导体基板上的氧化膜和形成在基底基板上的含氮层彼此结合。此外，在将形成在半导体衬底上的氧化膜和形成在基底衬底上的含氮层彼此粘合之前，对氧化物膜和含氮层中的至少一种进行等离子体处理。可以在施加偏置电压的状态下进行等离子体处理。

4. 发明申请

US20070037070A1 LIGHT EXPOSURE MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：光曝光掩模及使用其制造半导体器件的方法
公开(公告)号：US20070037070A1
公开(公告)日：2007-02-15
申请号：US11463147
申请日：2006-08-08
申请人： Hideto OHNUMA , Masaharu NAGAI
发明人： Hideto OHNUMA , Masaharu NAGAI
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： H01L27/1288 , G03F1/50 , H01L27/1214 , H01L27/124 , H01L27/127 , H01L29/42384 , H01L29/66757 , H01L29/78621
摘要： The present invention provides a light exposure mask which can form a photoresist layer in a semi-transmissive portion with uniform thickness, and a method for manufacturing a semiconductor device in which the number of photolithography steps (the number of masks) necessary for manufacturing a TFT substrate is reduced by using the light exposure mask. A light exposure mask is used, which includes a transmissive portion, a light shielding portion, and a semi-transmissive portion having a light intensity reduction function where lines and spaces are repeatedly formed, wherein the sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×m≦L+S≦(6n/5)×m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧1).
摘要翻译：本发明提供一种能够在均匀厚度的半透射部分中形成光致抗蚀剂层的曝光掩模，以及制造半导体器件的方法，其中制造TFT所需的光刻步骤数（掩模数）通过使用曝光掩模来减少衬底。使用曝光掩模，其包括透射部分，遮光部分和具有重复形成线和间隔的光强降低功能的半透射部分，其中遮光层的线宽L之和材料和半透射部分中的遮光材料之间的空间宽度S满足条件表达式（2n / 3）xm <= L + S <=（6n / 5）×m，当曝光装置的分辨率由 n，投影倍率由1 / m（m> = 1）表示。

5. 发明申请

US20120164817A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20120164817A1
公开(公告)日：2012-06-28
申请号：US13411864
申请日：2012-03-05
申请人： Takeshi SHICHI , Junichi KOEZUKA , Hideto OHNUMA , Shunpei YAMAZAKI
发明人： Takeshi SHICHI , Junichi KOEZUKA , Hideto OHNUMA , Shunpei YAMAZAKI
IPC分类号： H01L21/46
CPC分类号： H01L27/1266 , H01L21/76254 , H01L27/1214 , H01L29/66772
摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.
摘要翻译：本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

6. 发明申请

US20120007095A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120007095A1
公开(公告)日：2012-01-12
申请号：US13238754
申请日：2011-09-21
申请人： Shunpei YAMAZAKI , Satoshi MURAKAMI , Jun KOYAMA , Yukio TANAKA , Hidehito KITAKADO , Hideto OHNUMA
发明人： Shunpei YAMAZAKI , Satoshi MURAKAMI , Jun KOYAMA , Yukio TANAKA , Hidehito KITAKADO , Hideto OHNUMA
IPC分类号： H01L29/38
CPC分类号： G02F1/1368 , G02F1/133345 , G02F1/13454 , G02F1/136227 , G02F1/136286 , G02F2201/123 , G02F2202/104 , H01L27/12 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L27/1259 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L27/3272 , H01L27/3276 , H01L29/458 , H01L29/78621 , H01L29/78627 , H01L29/78675 , H01L2029/7863 , H01L2227/323
摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.
摘要翻译：本发明提供一种具有高操作性能和高可靠性的半导体器件。在形成驱动电路的n沟道TFT 802中配置与栅极配线重叠的LDD区域707，能够实现高耐热载流子注入的TFT结构。不与栅极布线重叠的LDD区域717,718,719和720被布置在形成像素单元的n沟道TFT 804中。结果，实现了具有小的截止电流值的TFT结构。在这种情况下，属于周期表第15族的元素在LDD区707中比在LDD区717,718,719和720中的浓度更高。

7. 发明申请

US20110068339A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110068339A1
公开(公告)日：2011-03-24
申请号：US12958739
申请日：2010-12-02
申请人： Toshimitsu KONUMA , Akira SUGAWARA , Yukiko UEHARA , Hongyong ZHANG , Atsunori SUZUKI , Hideto OHNUMA , Naoaki YAMAGUCHI , Hideomi SUZAWA , Hideki UOCHI , Yasuhiko TAKEMURA
发明人： Toshimitsu KONUMA , Akira SUGAWARA , Yukiko UEHARA , Hongyong ZHANG , Atsunori SUZUKI , Hideto OHNUMA , Naoaki YAMAGUCHI , Hideomi SUZAWA , Hideki UOCHI , Yasuhiko TAKEMURA
IPC分类号： H01L29/772 , H01L27/12
CPC分类号： H01L29/665 , H01L21/02145 , H01L21/02244 , H01L21/02258 , H01L21/31116 , H01L21/31144 , H01L21/31683 , H01L21/31687 , H01L21/321 , H01L27/124 , H01L27/127 , H01L29/458 , H01L29/66598 , H01L29/66757 , H01L29/78621 , H01L29/78627
摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
摘要翻译：形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。此后，进行一个导电性元素的离子掺杂。高电阻率区域限定在栅极绝缘膜下。

8. 发明申请

US20100244051A1 Semiconductor Device and Manufacturing Method Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100244051A1
公开(公告)日：2010-09-30
申请号：US12731699
申请日：2010-03-25
申请人： Hideto OHNUMA
发明人： Hideto OHNUMA
IPC分类号： H01L29/24 , H01L21/18
CPC分类号： H01L29/66068 , H01L21/76254 , H01L21/8213 , H01L21/84 , H01L27/12 , H01L29/1608 , H01L29/66651 , H01L29/66772 , H01L29/78684
摘要： An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer.
摘要翻译：本发明的目的是实现具有多种功能的半导体器件中的集成电路，或者即使当使用碳化硅衬底形成集成电路时也可以增加集成电路的尺寸。集成电路包括：第一晶体管，包括设置在基板上的岛状碳化硅层，其间插入有第一绝缘层，设置在碳化硅层上的第一栅极绝缘层，以及设置在第一栅极绝缘层上的第一导电层并与碳化硅层重叠; 以及第二晶体管，其包括设置在所述基板上的岛状单晶硅层，其间插入有第二绝缘层，设置在所述单晶硅层上的第二栅极绝缘层，以及设置在所述第二栅极绝缘层上的第二导电层并与单晶硅层重叠。

9. 发明申请

US20100096720A1 SOI SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： SOI衬底及其制造方法
公开(公告)号：US20100096720A1
公开(公告)日：2010-04-22
申请号：US12580532
申请日：2009-10-16
申请人： Hideto OHNUMA , Eiji HIGA
发明人： Hideto OHNUMA , Eiji HIGA
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76254
摘要： To provide an SOI substrate having a high mechanical strength, and a method for manufacturing the SOI substrate, a single crystal semiconductor substrate is irradiated with accelerated ions so that an embrittled region is formed in a region at a predetermined depth from a surface of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate with an insulating layer interposed therebetween; the single crystal semiconductor substrate is heated to be separated along the embrittled region, so that a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween; and a surface of the semiconductor layer is irradiated with a laser beam so that at least a superficial part of the semiconductor layer is melted, whereby at least one of nitrogen, oxygen, and carbon is solid-dissolved in the semiconductor layer.
摘要翻译：为了提供具有高机械强度的SOI衬底以及SOI衬底的制造方法，用加速离子照射单晶半导体衬底，使得在距离单个表面的表面预定深度的区域中形成脆化区域晶体半导体衬底; 将单晶半导体基板与绝缘层接合在基底基板上，单晶半导体衬底被加热以沿着脆化区域分离，从而在绝缘层之间设置在基底衬底上的半导体层; 并且用激光束照射半导体层的表面，使得至少半导体层的表面部分熔化，由此氮，氧和碳中的至少一个固体溶解在半导体层中。

10. 发明申请

US20090263942A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090263942A1
公开(公告)日：2009-10-22
申请号：US12420887
申请日：2009-04-09
申请人： Hideto OHNUMA , Noritsugu NOMURA
发明人： Hideto OHNUMA , Noritsugu NOMURA
IPC分类号： H01L21/336
CPC分类号： H01L21/76254 , H01L21/84 , H01L27/1233 , H01L29/78621
摘要： A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.
摘要翻译：将具有脆化层的单晶半导体基板安装在基板上，其间插入有绝缘层，并且通过热处理在脆化层处分离单晶半导体层; 因此，单晶半导体层固定在基底基板上。用激光束照射单晶半导体层，使得单晶半导体层部分熔融，然后重新单晶化，从而除去晶体缺陷。此外，用于形成n沟道晶体管的岛状单晶半导体层使用光掩模进行沟道掺杂，然后使用光掩模进行回蚀，从而形成用于形成n沟道晶体管的岛状单晶半导体层比用于形成p沟道晶体管的岛状单晶半导体层薄。

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