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    • 6. 发明授权
    • Pixel defect correction apparatus
    • 像素缺陷校正装置
    • US4701784A
    • 1987-10-20
    • US829135
    • 1986-01-31
    • Hiroki MatsuokaAtsushi MorimuraYoshinori Kitamura
    • Hiroki MatsuokaAtsushi MorimuraYoshinori Kitamura
    • H04N5/367H04N3/14
    • H04N5/367
    • A defect correction apparatus includes a memory having information of image failure of a solid state imaging device, a coincidence detection circuit for detecting a position of pixel having a failure at the time of image pick up, and a failure correction circuit. The failure correction circuit includes structure for producing plural signals for correction of signals of pixels around the pixel having the failure, and structure for selecting an optimum one from the produced plural signals, for correction responding to condition of the image and signals of the pixel therearound, and to use the selected optimum signal for correction by switching for the signal of the failure pixel.
    • PCT No.PCT / JP85 / 00300 Sec。 371日期1986年1月31日 102(e)日期1986年1月31日PCT提交1985年5月30日PCT公布。 公开号WO85 / 05752 日期:1985年12月19日。缺陷修正装置包括具有固态成像装置的图像故障信息的存储器,用于检测图像拾取时具有故障的像素的位置的重合检测电路和故障 校正电路。 故障校正电路包括用于产生用于校正具有故障的像素周围的像素的信号的多个信号的结构,以及用于从所产生的多个信号中选择最佳像素的结构,用于根据图像的条件和其周围的像素的信号进行校正 并且通过切换故障像素的信号来使用所选择的最佳信号进行校正。
    • 10. 发明授权
    • Semiconductor device and method of manufacturing the same
    • 半导体装置及其制造方法
    • US06969884B2
    • 2005-11-29
    • US10728928
    • 2003-12-08
    • Yoshinori KitamuraShigeki Sugimoto
    • Yoshinori KitamuraShigeki Sugimoto
    • H01L21/00H01L21/28H01L21/331H01L21/82H01L21/8222H01L21/8247H01L27/115H01L29/76H01L29/788H01L29/792
    • H01L27/11521H01L21/28273H01L27/115H01L27/11524
    • Disclosed is a semiconductor device comprising a semiconductor substrate including first and second element-formation regions partitioned by an isolation trench, first and second lower gate insulating films formed on the first and second element-formation regions, first and second floating gates formed on the first and second lower gate insulating films, an isolation insulating film formed at least in the isolation trench and has a depression formed in an upper surface thereof, an upper gate insulating film formed on the first and second floating gates, and a control gate line including an opposed portion opposed to the first and second floating gates, with the upper gate insulating film being interposed, and a portion located inside the depression, the first floating gate including a side surface opposed to the second floating gate and entirely aligns with a side surface included in the first element-formation region and defined by the isolation trench.
    • 公开了一种半导体器件,包括半导体衬底,该半导体衬底包括由隔离沟槽分隔开的第一和第二元件形成区域,形成在第一和第二元件形成区域上的第一和第二下部栅极绝缘膜,形成在第一和第二元件形成区域上的第一和第二浮置栅极 和第二下栅极绝缘膜,隔离绝缘膜,至少形成在所述隔离沟槽中,并且在其上表面上形成有凹部,形成在所述第一和第二浮栅上的上栅极绝缘膜,以及控制栅极线, 与第一和第二浮动栅极相对的相对部分,其中上部栅极绝缘膜被插入,并且位于凹部内部的部分,第一浮动栅极包括与第二浮动栅极相对的侧表面,并且与包括的侧表面完全对准 在第一元件形成区域中并由隔离沟槽限定。