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1. 发明申请

US20090267649A1 Clock Gating System and Method 有权
标题翻译：时钟门控系统和方法
公开(公告)号：US20090267649A1
公开(公告)日：2009-10-29
申请号：US12431992
申请日：2009-04-29
申请人： Martin Saint-Laurent , Bassam Jamil Mohd , Paul Bassett
发明人： Martin Saint-Laurent , Bassam Jamil Mohd , Paul Bassett
IPC分类号： H03K19/096 , H03K19/00
CPC分类号： H03K19/0016 , G06F1/04
摘要： A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.
摘要翻译：公开了时钟选通系统和方法。在特定实施例中，系统包括输入逻辑电路，该输入逻辑电路具有至少一个输入端以接收至少一个输入信号并在内部使能节点具有输出。保持器电路包括响应于门控时钟信号的至少一个开关元件，并且耦合到内部使能节点以选择性地保持内部使能节点处的逻辑电压电平。该系统还包括响应于输入时钟信号和内部使能节点处的逻辑电压电平的选通元件，以产生门控时钟信号。

2. 发明授权

US07902878B2 Clock gating system and method 有权
标题翻译：时钟门控系统和方法
公开(公告)号：US07902878B2
公开(公告)日：2011-03-08
申请号：US12431992
申请日：2009-04-29
申请人： Martin Saint-Laurent , Bassam Jamil Mohd , Paul Bassett
发明人： Martin Saint-Laurent , Bassam Jamil Mohd , Paul Bassett
IPC分类号： H03K19/096
CPC分类号： H03K19/0016 , G06F1/04
摘要： A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.
摘要翻译：公开了时钟选通系统和方法。在特定实施例中，系统包括输入逻辑电路，该输入逻辑电路具有至少一个输入端以接收至少一个输入信号并在内部使能节点具有输出。保持器电路包括响应于门控时钟信号的至少一个开关元件，并且耦合到内部使能节点以选择性地保持内部使能节点处的逻辑电压电平。该系统还包括响应于输入时钟信号和内部使能节点处的逻辑电压电平的选通元件，以产生门控时钟信号。

3. 发明授权

US07746137B2 Sequential circuit element including a single clocked transistor 有权
标题翻译：顺序电路元件包括单个时钟晶体管
公开(公告)号：US07746137B2
公开(公告)日：2010-06-29
申请号：US11845950
申请日：2007-08-28
申请人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
发明人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
IPC分类号： H03K3/356
CPC分类号： H03K3/356121 , G06F9/3869
摘要： A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.
摘要翻译：公开了一种方法，其包括响应于在顺序电路元件的单个时钟晶体管处接收的时钟信号，经由时序电路元件的第一数据路径传播数据。该方法还包括保持与在第二数据路径的保持电路元件处经由第一路径传播的数据有关的信息，其中第一数据路径包括响应于单个时钟晶体管的输出的第一晶体管。第一晶体管具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。

4. 发明授权

US07567096B2 Circuit device and method of controlling a voltage swing 有权
标题翻译：控制电压摆幅的电路装置及方法
公开(公告)号：US07567096B2
公开(公告)日：2009-07-28
申请号：US11843696
申请日：2007-08-23
申请人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
发明人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K19/096
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译：在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。该方法包括在包括电容性节点的数字电路装置的输入处接收信号。该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。在特定说明性实施例中，接收信号可以是时钟信号。

5. 发明申请

US20090058463A1 Sequential Circuit Element Including A Single Clocked Transistor 有权
标题翻译：包括单时钟晶体管的顺序电路元件
公开(公告)号：US20090058463A1
公开(公告)日：2009-03-05
申请号：US11845950
申请日：2007-08-28
申请人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
发明人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
IPC分类号： H03K3/02
CPC分类号： H03K3/356121 , G06F9/3869
摘要： A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.
摘要翻译：公开了一种方法，其包括响应于在顺序电路元件的单个时钟晶体管处接收的时钟信号，经由时序电路元件的第一数据路径传播数据。该方法还包括保持与在第二数据路径的保持电路元件处经由第一路径传播的数据有关的信息，其中第一数据路径包括响应于单个时钟晶体管的输出的第一晶体管。第一晶体管具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。

6. 发明申请

US20080231322A1 Circuit Device and Method of Controlling a Voltage Swing 有权
标题翻译：控制电压摆动的电路装置及方法
公开(公告)号：US20080231322A1
公开(公告)日：2008-09-25
申请号：US11843696
申请日：2007-08-23
申请人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
发明人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译：在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。该方法包括在包括电容性节点的数字电路装置的输入处接收信号。该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。在特定说明性实施例中，接收信号可以是时钟信号。

7. 发明申请

US20070300108A1 Logic device and method supporting scan test 有权
标题翻译：支持扫描测试的逻辑设备和方法
公开(公告)号：US20070300108A1
公开(公告)日：2007-12-27
申请号：US11473219
申请日：2006-06-22
申请人： Martin Saint-Laurent , Paul Bassett , Prayag Patel
发明人： Martin Saint-Laurent , Paul Bassett , Prayag Patel
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/3025 , G01R31/318575
摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
摘要翻译：逻辑器件包括数据输入，扫描测试输入，时钟解复用器和主锁存器。时钟解复用器响应于时钟输入以选择性地提供第一时钟输出和第二时钟输出。主锁存器耦合到数据输入和扫描测试输入，并包括输出。主锁存器响应于时钟解复用器的第一时钟输出和时钟解复用器的第二时钟输出，以选择性地将数据输入或扫描测试输入耦合到输出。

8. 发明授权

US07724058B2 Latch structure and self-adjusting pulse generator using the latch 有权
标题翻译：锁存结构和自调脉冲发生器
公开(公告)号：US07724058B2
公开(公告)日：2010-05-25
申请号：US11930915
申请日：2007-10-31
申请人： Martin Saint-Laurent , Paul Bassett
发明人： Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K3/00
CPC分类号： H03K3/037 , H03K3/356043 , H03K5/135
摘要： The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch.
摘要翻译：本公开包括使用锁存器的锁存结构和自调整脉冲发生器。在一个实施例中，系统包括第一锁存器和连接到第一锁存器的定时信号的脉冲发生器。脉冲发生器包括具有与第一锁存器匹配的特性的第二锁存器。

9. 发明申请

US20090108895A1 Latch Structure and Self-Adjusting Pulse Generator Using the Latch 有权
标题翻译：锁定结构和自调整脉冲发生器
公开(公告)号：US20090108895A1
公开(公告)日：2009-04-30
申请号：US11930915
申请日：2007-10-31
申请人： Martin Saint-Laurent , Paul Bassett
发明人： Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K5/04 , H03K3/00
CPC分类号： H03K3/037 , H03K3/356043 , H03K5/135
摘要： The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch.
摘要翻译：本公开包括使用锁存器的锁存结构和自调整脉冲发生器。在一个实施例中，系统包括第一锁存器和连接到第一锁存器的定时信号的脉冲发生器。脉冲发生器包括具有与第一锁存器匹配的特性的第二锁存器。

10. 发明授权

US07992062B2 Logic device and method supporting scan test 有权
标题翻译：支持扫描测试的逻辑设备和方法
公开(公告)号：US07992062B2
公开(公告)日：2011-08-02
申请号：US11473219
申请日：2006-06-22
申请人： Martin Saint-Laurent , Paul Bassett , Prayag Patel
发明人： Martin Saint-Laurent , Paul Bassett , Prayag Patel
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/3025 , G01R31/318575
摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
摘要翻译：逻辑器件包括数据输入，扫描测试输入，时钟解复用器和主锁存器。时钟解复用器响应于时钟输入以选择性地提供第一时钟输出和第二时钟输出。主锁存器耦合到数据输入和扫描测试输入，并包括输出。主锁存器响应于时钟解复用器的第一时钟输出和时钟解复用器的第二时钟输出，以选择性地将数据输入或扫描测试输入耦合到输出。

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