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1. 发明申请

US20100248446A1 METHOD AND APPARATUS OF HOLDING A DEVICE 有权
标题翻译：控制装置的方法和装置
公开(公告)号：US20100248446A1
公开(公告)日：2010-09-30
申请号：US12414861
申请日：2009-03-31
申请人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
发明人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
IPC分类号： H01L21/30 , B25B11/00
CPC分类号： H01L21/6838 , H01L21/304
摘要： Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.
摘要翻译：提供了一种保持装置的装置和方法。该装置包括具有穿过其延伸的第一和第二孔的晶片卡盘，以及压力控制结构，其能够在高于和低于环境压力的压力之间独立地和选择性地改变在第一和第二孔中的每一个中的流体压力。该方法包括提供具有延伸穿过其中的第一和第二孔的晶片卡盘，并且在高于和低于环境压力的压力之间独立地和选择性地改变在每个第一和第二孔中的流体压力。

2. 发明授权

US08851133B2 Method and apparatus of holding a device 有权
标题翻译：握持装置的方法和装置
公开(公告)号：US08851133B2
公开(公告)日：2014-10-07
申请号：US12414861
申请日：2009-03-31
申请人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
发明人： Martin Liu , Chung-Yi Yu , Che Ying Hsu , Yeur-Luen Tu , Da-Hsiang Chou , Chia-Shiung Tsai
IPC分类号： C23C16/50 , C23C16/00 , C23F1/00 , H01L21/306 , H01L21/683
CPC分类号： H01L21/6838 , H01L21/304
摘要： Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.
摘要翻译：提供了一种保持装置的装置和方法。该装置包括具有穿过其延伸的第一和第二孔的晶片卡盘，以及压力控制结构，其能够在高于和低于环境压力的压力之间独立地和选择性地改变在第一和第二孔中的每一个中的流体压力。该方法包括提供具有延伸穿过其中的第一和第二孔的晶片卡盘，并且在高于和低于环境压力的压力之间独立地和选择性地改变在每个第一和第二孔中的流体压力。

3. 发明申请

US20050215004A1 Method of forming MIM capacitor electrodes 有权
标题翻译：形成MIM电容器电极的方法
公开(公告)号：US20050215004A1
公开(公告)日：2005-09-29
申请号：US10811657
申请日：2004-03-29
申请人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
IPC分类号： H01G4/005 , H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/44 , H01L23/522 , H01L29/06
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.
摘要翻译：公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能，在MIM电容器的制造中。该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

4. 发明授权

US07199001B2 Method of forming MIM capacitor electrodes 有权
标题翻译：形成MIM电容器电极的方法
公开(公告)号：US07199001B2
公开(公告)日：2007-04-03
申请号：US10811657
申请日：2004-03-29
申请人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
IPC分类号： H01L21/8242
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.
摘要翻译：公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能，在MIM电容器的制造中。该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

5. 发明授权

US08173518B2 Method of wafer bonding 有权
标题翻译：晶圆接合方法
公开(公告)号：US08173518B2
公开(公告)日：2012-05-08
申请号：US12414910
申请日：2009-03-31
申请人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L21/30
CPC分类号： H01L27/1469 , H01L21/76256 , H01L27/14634 , H01L27/1464
摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.
摘要翻译：提供一种制造半导体器件的方法。该方法包括提供具有前侧，后侧和第一边缘部分的器件基板，在器件基板的正面的一部分的一部分上形成材料层，修整第一边缘部分，去除材料层，接合将器件基板的正面侧支撑到载体基板，从背面侧使器件基板变薄，以及修整变薄的器件基板的第二边缘部分。

6. 发明申请

US20100248414A1 METHOD OF WAFER BONDING 有权
标题翻译： WAFER BONDING的方法
公开(公告)号：US20100248414A1
公开(公告)日：2010-09-30
申请号：US12414910
申请日：2009-03-31
申请人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Martin Liu , Alex Hsu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L31/02 , H01L21/762 , H01L21/304
CPC分类号： H01L27/1469 , H01L21/76256 , H01L27/14634 , H01L27/1464
摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a device substrate having a front side, a back side, and a first edge portion, forming a material layer over a portion of the front side of the device substrate, trimming the first edge portion, removing the material layer, bonding the front side of the device substrate to a carrier substrate, thinning the device substrate from the back side, and trimming a second edge portion of the thinned device substrate.
摘要翻译：提供一种制造半导体器件的方法。该方法包括提供具有前侧，后侧和第一边缘部分的器件基板，在器件基板的正面的一部分的一部分上形成材料层，修整第一边缘部分，去除材料层，接合将器件基板的正面侧支撑到载体基板，从背面侧使器件基板变薄，以及修整变薄的器件基板的第二边缘部分。

7. 发明授权

US06780731B1 HDP gap-filling process for structures with extra step at side-wall 失效
标题翻译： HDP间隙填充过程，用于侧壁额外加工的结构
公开(公告)号：US06780731B1
公开(公告)日：2004-08-24
申请号：US10225803
申请日：2002-08-22
申请人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
发明人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.
摘要翻译：一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层沟。该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

8. 发明授权

US08809179B2 Method for reducing topography of non-volatile memory and resulting memory cells 有权
标题翻译：减少非易失性存储器和结果存储单元的形貌的方法
公开(公告)号：US08809179B2
公开(公告)日：2014-08-19
申请号：US11716164
申请日：2007-03-09
申请人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
发明人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
IPC分类号： H01L21/44 , H01L27/115 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11573
摘要： A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.
摘要翻译：一种形成半导体结构的方法包括：提供衬底; 形成闪存单元的栅极堆叠，其中所述栅极堆叠的顶部部分包括覆盖层; 形成具有覆盖层上方的至少一部分的栅极; 并且在所述封盖层上减小所述栅极的所述部分的厚度。闪存单元和同一芯片上的MOS器件之间的地形高差减小。

9. 发明申请

US20080217775A1 Method of forming contact plugs for eliminating tungsten seam issue 审中-公开
标题翻译：形成用于消除钨焊缝问题的接触塞的方法
公开(公告)号：US20080217775A1
公开(公告)日：2008-09-11
申请号：US11714770
申请日：2007-03-07
申请人： Chih-Yang Pai , Wen-Chuan Chiang , Chung-Yi Yu , Yeur-Luen Tu , Yuan-Hung Liu , Hsiang-Fan Lee , Chuan-Jong Wang
发明人： Chih-Yang Pai , Wen-Chuan Chiang , Chung-Yi Yu , Yeur-Luen Tu , Yuan-Hung Liu , Hsiang-Fan Lee , Chuan-Jong Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76849 , H01L27/10855 , H01L27/10888
摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.
摘要翻译：形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

10. 发明申请

US20070241386A1 Method for reducing topography of non-volatile memory and resulting memory cells 有权
标题翻译：减少非易失性存储器和结果存储单元的形貌的方法
公开(公告)号：US20070241386A1
公开(公告)日：2007-10-18
申请号：US11716164
申请日：2007-03-09
申请人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
发明人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11573
摘要： A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.
摘要翻译：一种形成半导体结构的方法包括：提供衬底; 形成闪存单元的栅极堆叠，其中所述栅极堆叠的顶部部分包括覆盖层; 形成具有覆盖层上方的至少一部分的栅极; 并且在所述封盖层上减小所述栅极的所述部分的厚度。闪存单元和同一芯片上的MOS器件之间的地形高差减小。

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