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1. 发明申请

US20080217775A1 Method of forming contact plugs for eliminating tungsten seam issue 审中-公开
标题翻译：形成用于消除钨焊缝问题的接触塞的方法
公开(公告)号：US20080217775A1
公开(公告)日：2008-09-11
申请号：US11714770
申请日：2007-03-07
申请人： Chih-Yang Pai , Wen-Chuan Chiang , Chung-Yi Yu , Yeur-Luen Tu , Yuan-Hung Liu , Hsiang-Fan Lee , Chuan-Jong Wang
发明人： Chih-Yang Pai , Wen-Chuan Chiang , Chung-Yi Yu , Yeur-Luen Tu , Yuan-Hung Liu , Hsiang-Fan Lee , Chuan-Jong Wang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76849 , H01L27/10855 , H01L27/10888
摘要： A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole.
摘要翻译：形成eDRAM器件的接触插塞的方法包括以下步骤：在电介质层上形成具有钨接缝的钨层以填充接触孔; 从电介质层的顶表面去除钨层，使接触孔中的钨层凹陷，以在电介质层的顶表面下方深度形成约600〜900埃的凹陷，在电介质层上沉积导电层和凹入的钨塞填充凹槽; 并且从电介质层的顶表面去除导电层，以在接触孔中的凹入的钨插塞上形成导电插塞。

2. 发明授权

US06780731B1 HDP gap-filling process for structures with extra step at side-wall 失效
标题翻译： HDP间隙填充过程，用于侧壁额外加工的结构
公开(公告)号：US06780731B1
公开(公告)日：2004-08-24
申请号：US10225803
申请日：2002-08-22
申请人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
发明人： Yeur-Luen Tu , Tsung-Hsun Huang , Chung-Yi Yu , Yuan-Hung Liu
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon first layer, an oxide second layer and a nitride third layer, wherein the nitride layer is pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without dam aging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the side walls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio and low bias power to form a layer with an overhang at the upper surface of the trench. This deposition if followed by a sputtering process to form an enlarged opening in that overhang. This approach is found to prevent the formation of an overhang at the position of the step, whereat it would cause progressive restriction of the trench throat and void formation.
摘要翻译：一种多步骤HDP沉积和溅射方法，用于无缝填充具有阶梯形横截面轮廓的高纵横比沟槽。该方法特别适用于填充形成在包括硅第一层，氧化物第二层和氮化物第三层的三层分层衬底中的沟槽，其中氮化物层从沟槽开口的边缘被拉回并形成一个台阶。该方法允许这种沟槽的无空隙填充，而不会使该过程中的氮化物层老化。简而言之，该方法的本质是在沟槽的侧壁上形成沉积层，其中第一层以高沉积至溅射比沉积，并且具有低偏压能力以在上表面形成具有突出端的层沟。该沉积如果随后是溅射工艺以在该突出端形成扩大的开口。发现这种方法可以防止在台阶位置形成突出端，从而导致沟槽喉部和空隙形成的逐渐限制。

3. 发明授权

US07824998B2 Method of forming a semiconductor capacitor using amorphous carbon 有权
标题翻译：使用无定形碳形成半导体电容器的方法
公开(公告)号：US07824998B2
公开(公告)日：2010-11-02
申请号：US12357661
申请日：2009-01-22
申请人： Yuan-Hung Liu , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Ming Chyi Liu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/20
CPC分类号： H01L21/02274 , H01L21/02115 , H01L21/28273 , H01L21/3086 , H01L21/31116 , H01L21/31144 , H01L21/3146 , H01L21/76816 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L27/115 , H01L27/11521 , H01L27/14632 , H01L27/14687 , H01L28/91 , H01L29/42328 , H01L29/7881
摘要： A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.
摘要翻译：一种方法包括在形成在衬底上的第一电介质层上形成无定形碳层，在非晶碳层上形成第二电介质层; 以及通过第一蚀刻工艺在所述非晶碳层和所述第二介电层内形成开口，以部分地暴露所述第一介电层的顶表面。在第二电介质层上并在开口内形成基本上共形的含金属层。去除第二电介质层和一部分含金属层。通过含氧等离子体工艺除去无定形碳层以暴露第一介电层的顶表面。在含金属层的上方形成有绝缘层，在绝缘层上形成第二含金属层，形成电容器。

4. 发明授权

US08889507B2 MIM capacitors with improved reliability 有权
标题翻译： MIM电容器具有更高的可靠性
公开(公告)号：US08889507B2
公开(公告)日：2014-11-18
申请号：US11765971
申请日：2007-06-20
申请人： Chih-Ta Wu , Jason Lee , Chung Chien Wang , Hsing-Lien Lin , Yu-Jen Wang , Yeur-Luen Tu , Chern-Yow Hsu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Lucy Chang , Chia-Lin Chen , Ming-Chih Tsai
发明人： Chih-Ta Wu , Jason Lee , Chung Chien Wang , Hsing-Lien Lin , Yu-Jen Wang , Yeur-Luen Tu , Chern-Yow Hsu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Lucy Chang , Chia-Lin Chen , Ming-Chih Tsai
IPC分类号： H01L21/8234 , H01L21/8244 , H01L49/02 , H01L27/108
CPC分类号： H01L27/10814 , H01L27/10852 , H01L28/40 , H01L28/75
摘要： A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.
摘要翻译：提供电容器及其形成方法。该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

5. 发明申请

US20070096230A1 Magnetic memory cells and manufacturing methods 有权
标题翻译：磁记忆体和制造方法
公开(公告)号：US20070096230A1
公开(公告)日：2007-05-03
申请号：US11610760
申请日：2006-12-14
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L43/00 , H01L29/82
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

6. 发明申请

US20050274968A1 Lens structures suitable for use in image sensors and method for making the same 有权
标题翻译：适用于图像传感器的镜头结构及其制作方法
公开(公告)号：US20050274968A1
公开(公告)日：2005-12-15
申请号：US10982978
申请日：2004-11-05
申请人： Ching-Sen Kuo , Feng-Jia Shiu , Gwo-Yuh Shiau , Jieh-Jang Chen , Shih-Chi Fu , Chien Tseng , Chia-Shiung Tsai , Yuan-Hung Liu , Yeur-Luen Tu , Chih-Ta Wu , Chi-Hsin Lo
发明人： Ching-Sen Kuo , Feng-Jia Shiu , Gwo-Yuh Shiau , Jieh-Jang Chen , Shih-Chi Fu , Chien Tseng , Chia-Shiung Tsai , Yuan-Hung Liu , Yeur-Luen Tu , Chih-Ta Wu , Chi-Hsin Lo
IPC分类号： H01L21/00 , H01L27/146 , H01L29/04 , H01L29/06 , H01L29/10 , H01L29/22 , H01L29/227 , H01L31/036 , H01L31/0376 , H01L31/20 , H01L33/00 , H01L47/02
CPC分类号： H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L27/14687
摘要： An image sensor includes a double-microlens structure with an outer microlens aligned over an inner microlens, both microlenses aligned over a corresponding photosensor. The inner or outer microlens may be formed by a silylation process in which a reactive portion of a photoresist material reacts with a silicon-containing agent. The inner or outer microlens may be formed by step etching of a dielectric material, the step etching process including a series of alternating etch steps including an anisotropic etching step and an etching step that causes patterned photoresist to laterally recede. Subsequent isotropic etching processes may be used to smooth the etched step structure and form a smooth lens. A thermally stable and photosensitive polymeric/organic material may also be used to form permanent inner or outer lenses. The photosensitive material is coated then patterned using photolithography, reflowed, then cured to form a permanent lens structure.
摘要翻译：图像传感器包括双微透镜结构，其外部微透镜在内部微透镜上对准，两个微透镜在相应的光电传感器上对准。内部或外部微透镜可以通过甲硅烷基化方法形成，其中光致抗蚀剂材料的反应性部分与含硅试剂反应。内部或外部微透镜可以通过介电材料的步骤蚀刻形成，该步骤蚀刻工艺包括一系列交替蚀刻步骤，其包括各向异性蚀刻步骤和使图案化光致抗蚀剂横向后退的蚀刻步骤。可以使用随后的各向同性蚀刻工艺来平滑蚀刻的台阶结构并形成光滑的透镜。热稳定和感光的聚合物/有机材料也可用于形成永久的内镜片或外镜片。感光材料被涂覆，然后使用光刻图案化，回流，然后固化以形成永久性透镜结构。

7. 发明授权

US06869837B1 Methods of fabricating a word-line spacer for wide over-etching window on outside diameter (OD) and strong fence 失效
标题翻译：在外径（OD）和强栅栏上制作用于宽过度蚀刻窗口的字线间隔件的方法
公开(公告)号：US06869837B1
公开(公告)日：2005-03-22
申请号：US10758316
申请日：2004-01-15
申请人： Yuan-Hung Liu , Yeur-Luen Tu , Chin-Ta Wu , Tsung-Hsun Huang , Hsiu Ouyang , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Yeur-Luen Tu , Chin-Ta Wu , Tsung-Hsun Huang , Hsiu Ouyang , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/8238 , H01L21/8247 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer. Then etching: away the exposed portions of the conductive layer over the substrate; and through at least a portion of the thinned oxide layer and into the exposed underlying portion of the conductive layer to expose a portion of the inchoate split-gate flash memory structure and to form the word-line spacers adjacent the inchoate split-gate flash memory structure.
摘要翻译：一种制造字线间隔物的方法，包括以下步骤。提供了具有形成在其上的初始分离栅闪存结构的衬底。导电层形成在衬底和初生分裂栅极闪存结构之上。所述导电层具有：上部分裂栅极闪存结构上方的上部和下部垂直部分; 并且在基底上下方水平部分。在导电层之上形成双层氧化物层，并且在导电层的上部上具有更大的厚度。将氧化层部分地回蚀刻以从导电层的下部水平部分上方至少去除氧化物层，以暴露导电层的下面部分。然后蚀刻：将导电层的暴露部分远离衬底; 并且通过至少一部分减薄的氧化物层并进入导电层的暴露的下面的部分，以暴露初步分离栅闪存结构的一部分并且形成邻近先驱分离栅闪存的字线间隔物结构体。

8. 发明授权

US06177307B1 Process of planarizing crown capacitor for integrated circuit 有权
标题翻译：平面化集成电路的冠电容器的过程
公开(公告)号：US06177307B1
公开(公告)日：2001-01-23
申请号：US09392158
申请日：1999-09-08
申请人： Yeur-Luen Tu , Yuan-Hung Liu
发明人： Yeur-Luen Tu , Yuan-Hung Liu
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10888 , H01L28/87
摘要： A method for fabricating an integrated circuit having a cell area and a peripheral circuit area in a semiconductor substrate is disclosed. First, a memory device and a transistor are formed within the cell area and the peripheral circuit area, respectively, wherein the memory device has a doped region formed in the semiconductor substrate. Then, a first insulating layer is formed to overlie the cell area and the peripheral circuit area, and thereafter patterned to be a trench over the doped region and a recess in the peripheral circuit area. Next, the first insulating layer is patterned through the trench to form a contact window, and a landing plug is filled into the contact window in contact with the doped region. Subsequently, a second insulating layer and a third insulating layer are sequentially formed to overlie the cell area and the peripheral circuit area, and then patterned to form an opening over the doped region. Next, a first conductive layer is formed on the bottom and sidewall of the opening in contact with the landing plug. Then, the third insulating layer in the cell area is removed by a planarization process, and the second insulating layer in the cell area is thereafter removed. Finally, a dielectric layer and a second conductive layer are sequentially formed over the first conductive layer.
摘要翻译：公开了一种在半导体衬底中制造具有单元区域和外围电路区域的集成电路的方法。首先，存储器件和晶体管分别形成在单元区域和外围电路区域中，其中存储器件具有形成在半导体衬底中的掺杂区域。然后，形成第一绝缘层以覆盖电池区域和外围电路区域，然后将图案化为掺杂区域上的沟槽和外围电路区域中的凹部。接下来，通过沟槽图案化第一绝缘层以形成接触窗，并且将着陆塞填充到与掺杂区接触的接触窗中。随后，顺序地形成第二绝缘层和第三绝缘层，以覆盖电池区域和外围电路区域，然后构图以在掺杂区域上形成开口。接下来，第一导电层形成在与着陆塞接触的开口的底部和侧壁上。然后，通过平坦化处理去除单元区域中的第三绝缘层，然后除去单元区域中的第二绝缘层。最后，在第一导电层上依次形成电介质层和第二导电层。

9. 发明授权

US07554145B2 Magnetic memory cells and manufacturing methods 有权
标题翻译：磁记忆体和制造方法
公开(公告)号：US07554145B2
公开(公告)日：2009-06-30
申请号：US11610760
申请日：2006-12-14
申请人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Lan-Lin Chao , Yeur-Luen Tu , Wen-Chin Lin , Chia-Shiung Tsai
IPC分类号： H01L29/76
CPC分类号： H01L43/12 , H01L27/228
摘要： An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.
摘要翻译：改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。然后可以在掩模层和导电通孔上形成导电存储器线。

10. 发明授权

US07202130B2 Spacer for a split gate flash memory cell and a memory cell employing the same 有权
标题翻译：分离栅闪存单元的间隔器和采用其的存储单元
公开(公告)号：US07202130B2
公开(公告)日：2007-04-10
申请号：US10775290
申请日：2004-02-10
申请人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.
摘要翻译：间隔物，分裂栅极闪存单元及其相关方法。在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

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