专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5522088A Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus 失效
标题翻译：共享信道子系统具有使用接收到的时钟信号的自定时接口，以对从并行总线接收的位进行单独的相位对准
公开(公告)号：US5522088A
公开(公告)日：1996-05-28
申请号：US261641
申请日：1994-06-17
申请人： Marten J. Halma , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , Martin W. Sachs
发明人： Marten J. Halma , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , Martin W. Sachs
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/405
摘要： A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.
摘要翻译：共享信道子系统具有用于通过自定义接口（STI）将多个输入 - 输出控制器中的每一个耦合到多个处理器节点中的每一个的输入 - 输出元件，其中时钟信号将位串行数据时钟并行的导电总线，并且时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对齐，提供了一个经济有效的模块化输入/输出元件。

2. 发明授权

US5513377A Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus 失效
标题翻译：输入输出元件具有使用接收的时钟信号的自定时接口，以对从并行总线接收的单独的相位对准位
公开(公告)号：US5513377A
公开(公告)日：1996-04-30
申请号：US261561
申请日：1994-06-17
申请人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
发明人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
IPC分类号： H04L29/00 , G06F13/42 , H04L7/00 , G06F13/00
CPC分类号： G06F13/423
摘要： An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.
摘要翻译：增强的输入 - 输出元件具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准，以提供经济有效的模块化宽带输入/输出元件，可以经济地服务于两个通道，并可模块化地扩展以提供数百个通道。

3. 发明授权

US5598442A Self-timed parallel inter-system data communication channel 失效
标题翻译：自定时并行系统间数据通信通道
公开(公告)号：US5598442A
公开(公告)日：1997-01-28
申请号：US261522
申请日：1994-06-17
申请人： Thomas A. Gregg , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo
发明人： Thomas A. Gregg , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo
IPC分类号： G06F13/42 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L12/56 , H04L25/14 , H04L25/49 , H04L29/06
CPC分类号： H04L29/06 , G06F13/4278 , H04L25/14 , H04L25/4908 , H04L7/041 , H04L2007/045 , H04L69/14 , H04L7/0008
摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.
摘要翻译：自定义接口（STI）链接两个物理上分离的系统或节点。发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。

4. 发明授权

US5577078A Edge detector 失效
标题翻译：边缘检测器
公开(公告)号：US5577078A
公开(公告)日：1996-11-19
申请号：US452446
申请日：1995-05-26
申请人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
发明人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
IPC分类号： H03L7/06 , H04L7/033 , H04L7/04 , H04L7/00
CPC分类号： H04L7/0338
摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.
摘要翻译：边缘检测器具有数字锁相环，其中信号之一（例如，数据信号）耦合到产生输入的一系列增量相位延迟版本的延迟链。选择相邻相位延迟对，每次一对，并与另一个信号（例如，时钟信号）进行比较，以确定时钟的边沿是否落在所选相位对中的数据信号的边沿之间，或在所选相位对的边缘之外，在其一侧或另一侧上。如果时钟沿落在所选择的对之外，则控制信号选择另一对进行比较，并且重复处理，直到例如数据沿与时钟的正向边对齐。在时钟频率等于两倍数据频率的情况下，可以在时钟的下降沿对数据进行采样。

5. 发明授权

US5487095A Edge detector 失效
公开(公告)号：US5487095A
公开(公告)日：1996-01-23
申请号：US262087
申请日：1994-06-17
申请人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
发明人： Richard C. Jordan , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , William C. Laviola , Peter R. Tomaszewski
IPC分类号： H03L7/06 , H04L7/033 , H04L7/04 , H04L7/00
CPC分类号： H04L7/0338
摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

6. 发明授权

US5568526A Self timed interface 失效
标题翻译：自定义界面
公开(公告)号：US5568526A
公开(公告)日：1996-10-22
申请号：US452445
申请日：1995-05-26
申请人： Frank D. Ferraiolo , Robert S. Capowski , Daniel F. Casper , Richard C. Jordan , William C. Laviola
发明人： Frank D. Ferraiolo , Robert S. Capowski , Daniel F. Casper , Richard C. Jordan , William C. Laviola
IPC分类号： G06F13/42 , H04L7/00 , H04L7/033 , H04B1/10
CPC分类号： H04L7/0338 , G06F13/4256 , H04L7/0008
摘要： A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
摘要翻译：自定时接口（STI），其中时钟信号将串行数据时钟位于并行导电总线上，并且时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准。所接收的时钟信号用于为每条线分别定义数据位单元的边界，并且总线的每条线上的数据被单独相位调整，使得例如数据转换位置位于单元的中心。

7. 发明授权

US5548791A Input/output control system with plural channel paths to I/O devices 失效
标题翻译： I / O控制系统，用于基于其状态和其相关联的信道队列的可用时隙选择性地将工作分配给可用信道。
公开(公告)号：US5548791A
公开(公告)日：1996-08-20
申请号：US279581
申请日：1994-07-25
申请人： Daniel F. Casper , Steven G. Glassen , Marten J. Halma , Sandra K. Ryan
发明人： Daniel F. Casper , Steven G. Glassen , Marten J. Halma , Sandra K. Ryan
IPC分类号： G06F13/12 , G06F13/14
CPC分类号： G06F13/122
摘要： A data processing system includes a host processor and host memory means. The processor interacts with a plurality of peripheral units through an I/O system that includes a plurality of channels, one or more I/O processors (IOP's), and control data in a system area of the host memory means. Each channel has an associated busy bit in a vector, and is provided with a one position queue for dispatching work to the channel. Each queue has a bit in a vector indicating its full or empty status. A very efficient algorithm for the assignment of work for peripherals by the IOP's is provided in a system that provides for multiple paths through multiple channels between the host and a particular peripheral using the busy vector and queue vector.
摘要翻译：数据处理系统包括主机处理器和主机存储器装置。处理器通过包括多个信道，一个或多个I / O处理器（IOP）的I / O系统和主机存储器装置的系统区域中的控制数据与多个外围设备进行交互。每个通道在向量中都有一个相关联的忙位，并且具有一个位置队列，用于将工作调度到通道。每个队列都有一个向量中的位，表示其全部或空的状态。在通过忙向量和队列向量提供主机与特定外设之间的多个通道的多个路径的系统中提供了用于由IOP为外围设备分配工作的非常有效的算法。

8. 发明授权

US4604709A Channel communicator 失效
标题翻译：频道通讯员
公开(公告)号：US4604709A
公开(公告)日：1986-08-05
申请号：US465952
申请日：1983-02-14
申请人： Frederick T. Blount , Robert S. Capowski , Daniel F. Casper , Lawrence R. DelSonno , Robert F. Geller , Joseph M. Kusmiss , Terrence K. Zimmerman
发明人： Frederick T. Blount , Robert S. Capowski , Daniel F. Casper , Lawrence R. DelSonno , Robert F. Geller , Joseph M. Kusmiss , Terrence K. Zimmerman
IPC分类号： G06F13/12 , H04L29/02 , G06F13/14 , G06F13/38
CPC分类号： G06F13/126
摘要： A channel communicator CC has a storage array for holding an entry for each channel and for holding a busy vector and an interrupt vector that each have a bit for each channel. The CC is connected between the input bus and the output bus that connect the channels and an I/O processor IOP to processor main store. A message to the CC includes the ID of the channel that the message is to or from and the CC uses this ID as an address for accessing a channel entry or a bit in a vector. The message also carries a command that controls the CC to store a data portion of a message or to fetch a channel entry or a vector from the array and load it onto the output bus addressed to the IOP or to one of the channels. The command also controls addressing a particular one of the vectors. The CC also has means responsive to a command to perform a sequence of operations for testing the vectors and for testing fields of an entry in the array and for using the results of the test to control the execution of the command.
摘要翻译：信道通信器CC具有存储阵列，用于保存每个信道的条目，并且用于保存忙向量和每个具有每个信道的位的中断向量。 CC连接在输入总线和连接通道的输出总线和I / O处理器IOP到处理器主存储器之间。向CC发送的消息包括消息所在信道的ID，CC使用该ID作为访问信道条目的地址或向量中的位。该消息还携带控制CC以存储消息的数据部分的命令，或从阵列中获取信道条目或向量，并将其加载到寻址到IOP或其中一个信道的输出总线上。该命令还控制寻址一个特定的向量。 CC还具有响应于命令来执行用于测试向量的操作序列和用于测试阵列中条目的字段以及使用测试结果来控制命令的执行的装置。

9. 发明授权

US5526484A Method and system for pipelining the processing of channel command words 失效
标题翻译：流水线处理通道命令字的方法和系统
公开(公告)号：US5526484A
公开(公告)日：1996-06-11
申请号：US988549
申请日：1992-12-10
申请人： Daniel F. Casper , John A. deVeer , Edward Loizides , Martin W. Sachs , John H. Sorg, Jr.
发明人： Daniel F. Casper , John A. deVeer , Edward Loizides , Martin W. Sachs , John H. Sorg, Jr.
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A method and system for pipelining the processing of channel command words is provided. The channel is permitted to send commands and data to the control unit for several channel command words associated with a channel program without having to wait for responses from the control unit for prior commands sent. The channel can pipeline several commands to the control unit and the control unit can then process the commands in the order it receives them. The control unit sends responses to the channel for each command it receives acknowledging receipt of the commands.
摘要翻译：提供了一种用于流水线处理通道命令字的方法和系统。允许信道向控制单元发送与频道节目相关联的多个频道命令字的命令和数据，而不必等待来自控制单元的响应以发送先前的命令。该通道可以将多个命令管线到控制单元，然后控制单元可以按照接收命令的顺序处理命令。控制单元向接收到的每个命令的响应发送确认接收命令。

10. 发明授权

US09052837B2 Processing communication data in a ships passing condition 有权
标题翻译：处理船舶通行条件下的通信数据
公开(公告)号：US09052837B2
公开(公告)日：2015-06-09
申请号：US12031182
申请日：2008-02-14
申请人： Catherine C. Huang , Daniel F. Casper , John R. Flanagan , Roger G. Hathorn , Matthew J. Kalos , Louis W. Rcci
发明人： Catherine C. Huang , Daniel F. Casper , John R. Flanagan , Roger G. Hathorn , Matthew J. Kalos , Louis W. Rcci
IPC分类号： G06F3/00 , G06F3/06
CPC分类号： G06F13/4027 , G06F3/0607 , G06F3/0619 , G06F3/0659 , G06F3/0661 , G06F3/0689 , G06F13/28
摘要： Articles of manufacture, apparatuses, and methods for processing communications between a control unit and a channel subsystem in an input/output processing system are disclosed. Embodiments of the invention include an article of manufacture including at least one computer usable medium having computer readable program code logic to processing communications between a control unit and a channel subsystem in an input/output processing system. The computer readable program code logic performs a method including: sending a message in a first mode from the control unit to the channel subsystem; receiving a command in a second mode from the channel subsystem at the control unit; determining whether the command is responsive to the message; and responsive to the command being not responsive to the message, determining whether to perform one of i) executing the command and ii) terminating the command.
摘要翻译：公开了用于在输入/输出处理系统中处理控制单元和通道子系统之间的通信的制造，设备和方法。本发明的实施例包括一种制品，其包括具有计算机可读程序代码逻辑的至少一个计算机可用介质，以在输入/输出处理系统中处理控制单元和通道子系统之间的通信。计算机可读程序代码逻辑执行一种方法，包括：以第一模式从控制单元向通道子系统发送消息; 在所述控制单元处从所述通道子系统接收第二模式的命令; 确定所述命令是否响应于所述消息; 并且响应于所述命令不响应所述消息，确定是否执行i）执行所述命令和ii）终止所述命令之一。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式