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    • 1. 发明授权
    • Loop configured data transmission system
    • 环路配置数据传输系统
    • US4195351A
    • 1980-03-25
    • US872853
    • 1978-01-27
    • Robert P. BarnerAnne M. GulickJohn A. deVeerJan G. Oblonsky
    • Robert P. BarnerAnne M. GulickJohn A. deVeerJan G. Oblonsky
    • H04J3/24H04L5/22H04L12/433H04L12/437G06F15/16
    • H04L12/433H04L12/437
    • A data transmission system which includes stations connected in a closed loop configuration with interface capabilities at each station to connect to an external data processor. Through this configuration simultaneous transmission of data among processors connected to stations on the loop can be carried out by transmission of data around the loop between particular stations. Data is transmitted from a first processor to its individual station connected to the loop. This first station formats the data received from the first processor into frames of multi-bit configuration which are transmitted around the loop to a second station which is connected to a second processor. Data received by the second station is stored and transmitted to the second processor. During the time that this transmission from the first processor to the second processor is being carried out a transmission between other processors connected to stations on the loop can also be carried out. Each station on the loop receives all frames being serially transmitted around the loop and after examination of the address section of the frame will keep frames designated for that particular station and will pass on those frames addressed to other stations on the loop. Each of the stations connected in the loop is an identical unit including a clock generator and synchronizer with no master station being designated for control functions, therefore, no control lines other than a clock timing line are included in the loop. A bypass function selects an alternate path around a station on the loop to permit faulty stations to temporarily be disconnected from the loop bus. Each station has a purging capability which permits frames which have parity errors or illegitimate addresses to be removed from the loop.
    • 一种数据传输系统,其包括以闭环配置连接的站,在每个站处具有接口能力以连接到外部数据处理器。 通过这种配置,可以通过在特定站之间的循环周围的数据传输来执行连接到环路上的站的处理器之间的数据的同时传输。 数据从第一处理器发送到连接到回路的其各个站。 该第一站将从第一处理器接收的数据格式化成多个循环周期传送到连接到第二处理器的第二站的多位配置的帧。 由第二站接收的数据被存储并发送到第二处理器。 在执行从第一处理器到第二处理器的传输的时间期间,也可以执行连接到环路上的站之间的其它处理器之间的传输。 回路上的每个站都接收到围绕循环串行发送的所有帧,并且在帧的地址部分的检查之后将保留为该特定站指定的帧,并且将通过寻址到环路上的其他站的那些帧。 在循环中连接的每个站是包括时钟发生器和同步器的相同单元,没有为控制功能指定主站,因此在循环中不包括除时钟定时线之外的控制线。 旁路功能选择环路上的站周围的备用路径,以允许故障站暂时与环路总线断开连接。 每个站具有清除能力,允许从循环中移除具有奇偶校验错误或非法地址的帧。
    • 2. 发明授权
    • Distributed priority resolution system
    • 分布式优先级分辨率系统
    • US4320502A
    • 1982-03-16
    • US879987
    • 1978-02-22
    • John A. deVeer
    • John A. deVeer
    • G06F15/16G06F13/00G06F13/26G06F13/368G06F13/372G06F13/374G06F15/177H04J3/16H04J3/24H04J6/02
    • G06F13/26G06F13/372
    • Multiple stations exchange information without central supervision. Stations requiring a cycle of access time on a shared time-divided bus participate in a cyclic access resolution process. The station having highest priority for a next bus cycle indicates its precedence to the other stations, and assumes exclusive use of the bus in the next cycle. The bus may comprise separate sections for data and response communications. Separate access resolution processes are conducted relative to each section. After gaining access to the bus for one cycle of data transfer a station becomes ineligible to compete for access to the data section until it receives an associated response. Accordingly receiving stations may control both the rate of data transmittal and the rate of access competition activity at associated origin stations. The data and response communications may include address information for enabling stations to intercommunicate directly in pairs. Data processing stations subject to multi-level interruption may present control signals designating acceptable interruption priority levels. Other stations seeking to interrupt such processing stations are eligible to compete for access to the bus only if assigned interruption priorities are at designated levels.
    • 多个站点在没有中央监督的情况下交换信息。 在共享时分总线上需要访问时间周期的站参与循环访问解析过程。 对下一个总线周期具有最高优先级的站表示其优先于其他站,并且在下一周期中假定专用于总线。 总线可以包括用于数据和响应通信的单独部分。 相对于每个部分进行单独的访问解析过程。 在访问总线一周期的数据传输之后,一个站变得不符合竞争访问数据段的资格,直到它收到相关的响应。 因此,接收站可以控制数据传输的速率和相关原始站处的访问竞争活动的速率。 数据和响应通信可以包括用于使站能够成对直接相互通信的地址信息。 经受多级中断的数据处理站可能会提供指定可接受的中断优先级的控制信号。 其他试图中断这些处理站的站只有在指定的中断优先级处于指定级别时才有资格竞争访问总线。