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1. 发明申请

US20120058362A1 METHOD FOR DEPOSITING METAL ON A SUBSTRATE; METAL STRUCTURE AND METHOD FOR PLATING A METAL ON A SUBSTRATE 审中-公开
标题翻译：在基材上沉积金属的方法; 金属结构和金属在基材上的方法
公开(公告)号：US20120058362A1
公开(公告)日：2012-03-08
申请号：US12877118
申请日：2010-09-08
申请人： Markus Zistler , Stephan Bradl
发明人： Markus Zistler , Stephan Bradl
IPC分类号： B32B15/01 , B05D3/10
CPC分类号： C23C28/023 , C23C18/1651 , C23C18/1692 , C23C18/1841 , Y10T428/12646
摘要： Various embodiments provide a method for depositing metal on a substrate. The method may include carrying out a first immersion plating process, thereby forming a first metal portion on the substrate; providing an immersion plating activating substance on the first metal portion; and carrying out a second immersion plating process using the immersion plating activating substance, thereby forming a second metal portion on the first metal portion.
摘要翻译：各种实施例提供了一种在衬底上沉积金属的方法。该方法可以包括进行第一浸镀工艺，从而在衬底上形成第一金属部分; 在第一金属部分上提供浸镀活化物质; 并使用浸镀活化物质进行第二浸镀处理，从而在第一金属部分上形成第二金属部分。

2. 发明授权

US08309454B2 Structure for electrostatic discharge in embedded wafer level packages 有权
标题翻译：嵌入式晶圆级封装中的静电放电结构
公开(公告)号：US08309454B2
公开(公告)日：2012-11-13
申请号：US11746936
申请日：2007-05-10
申请人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
发明人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
IPC分类号： H01L21/4763
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/48 , H01L23/5389 , H01L23/552 , H01L23/60 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1617 , H01L2924/181 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
摘要翻译：工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

3. 发明授权

US07687895B2 Workpiece with semiconductor chips and molding, semiconductor device and method for producing a workpiece with semiconductors chips 有权
标题翻译：具有半导体芯片和模制的工件，半导体器件和用于制造具有半导体芯片的工件的方法
公开(公告)号：US07687895B2
公开(公告)日：2010-03-30
申请号：US11939938
申请日：2007-11-14
申请人： Markus Brunnbauer , Jens Pohl , Klaus Pressel , Thorsten Meyer , Recai Sezi , Stephan Bradl , Ralf Plieninger
发明人： Markus Brunnbauer , Jens Pohl , Klaus Pressel , Thorsten Meyer , Recai Sezi , Stephan Bradl , Ralf Plieninger
IPC分类号： H01L23/02 , H01L23/043 , H01L23/10 , H01L23/34 , H01L23/48 , H01L23/52 , H01L29/40 , H01L23/28
CPC分类号： H01L23/552 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/60 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/056 , H01L2224/12105 , H01L2224/82039 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/82 , H01L2924/00 , H01L2224/05099
摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also includes an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.
摘要翻译：工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。工件还包括布置在至少两个半导体芯片上的导电层，导电层至少布置在第二主表面的区域上，以及配置在导电层上的模塑料。在模塑料中配置有接触孔。

4. 发明授权

US06447372B1 Polishing agent for semiconductor substrates 有权
标题翻译：半导体衬底抛光剂
公开(公告)号：US06447372B1
公开(公告)日：2002-09-10
申请号：US09491296
申请日：2000-01-25
申请人： Stephan Bradl , Olaf Heitzsch
发明人： Stephan Bradl , Olaf Heitzsch
IPC分类号： B24B100
CPC分类号： C09K3/1463
摘要： The polishing agent of the invention has polishing grains suspended in a solution. The polishing grains consist essentially of a first substance with a glass transition temperature TG, and the polishing grains contain a dopant. The concentration of the dopant is set so that the glass transition temperature TG′ of the doped substance is lower than the glass transition temperature TG of the undoped first substance. The polishing agent is advantageously used for the microscratch-free planarization of a semiconductor substrate or of layers applied on it.
摘要翻译：本发明的抛光剂具有悬浮在溶液中的抛光颗粒。抛光颗粒基本上由具有玻璃化转变温度TG的第一物质组成，并且抛光颗粒含有掺杂剂。掺杂剂的浓度设定为使得掺杂物质的玻璃化转变温度TG'低于未掺杂的第一物质的玻璃化转变温度TG。抛光剂有利地用于半导体衬底或其上施加的层的无显微镜的平面化。

5. 发明授权

US08173534B2 Method for producing a semiconductor wafer with rear side identification 有权
标题翻译：用于制造具有背面识别的半导体晶片的方法
公开(公告)号：US08173534B2
公开(公告)日：2012-05-08
申请号：US13036669
申请日：2011-02-28
申请人： Stephan Bradl , Rainer Holmer
发明人： Stephan Bradl , Rainer Holmer
IPC分类号： H01L21/44
CPC分类号： H01L23/544 , H01L2223/5442 , H01L2223/54433 , H01L2223/54453 , H01L2223/54466 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
摘要翻译：公开了具有背面识别的半导体晶片及其制造方法。在一个实施例中，后侧识别具有关于单晶和表面以及后侧结构的多个信息。在半导体晶片的顶侧设置有以行和列排列的多个半导体器件位置，信息芯片布置在暴露的半导体器件位置，信息芯片至少具有背面识别信息。

6. 发明申请

US20080265383A1 Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips 有权
标题翻译：具有半导体芯片的工件，半导体器件和用半导体芯片生产工件的方法
公开(公告)号：US20080265383A1
公开(公告)日：2008-10-30
申请号：US11939938
申请日：2007-11-14
申请人： Markus Brunnbauer , Jens Pohl , Klaus Pressel , Thorsten Meyer , Recai Sezi , Stephan Bradl , Ralf Plieninger
发明人： Markus Brunnbauer , Jens Pohl , Klaus Pressel , Thorsten Meyer , Recai Sezi , Stephan Bradl , Ralf Plieninger
IPC分类号： H01L23/552 , H01L21/56
CPC分类号： H01L23/552 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/60 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/056 , H01L2224/12105 , H01L2224/82039 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/82 , H01L2924/00 , H01L2224/05099
摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer. In the molding compound a contact via is arranged.
摘要翻译：工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。在模塑料中配置有接触孔。

7. 发明申请

US20060276010A1 Arrangement of electronic semiconductor components on a carrier system for treating said semiconductor components with a liquid medium 有权
公开(公告)号：US20060276010A1
公开(公告)日：2006-12-07
申请号：US11438906
申请日：2006-05-23
申请人： Stephan Bradl , Michael Melzl , Josef Schwaiger , Thilo Stache
发明人： Stephan Bradl , Michael Melzl , Josef Schwaiger , Thilo Stache
IPC分类号： A23G3/20 , H01L21/00
CPC分类号： H01L21/67075 , H01L21/6704 , H01L21/6835
摘要： The invention relates to an arrangement of electronic semiconductor components on a carrier system for treating the semiconductor components with a liquid medium. A semiconductor component is detachably mounted on the carrier system with the active side thereof in such a way that the arrangement comprises a gap at least in the edge region and partially between the semiconductor components and the carrier system. The aim of the invention is to provide a detachable arrangement of electronic semiconductor components on a mechanically stable carrier system for safely handling the semiconductor components during the production process, wherein the capillarity of the gap between the semiconductor components and the carrier system is reduced in a controlled manner, thus preventing the damaging effect of a liquid medium seeping into the gap. To this end, the surface of the carrier system is shaped in such a way that the gap is widened along the entire edge region thereof.

8. 发明授权

US06337255B1 Method for forming a trench structure in a silicon substrate 有权
标题翻译：在硅衬底中形成沟槽结构的方法
公开(公告)号：US06337255B1
公开(公告)日：2002-01-08
申请号：US09535648
申请日：2000-03-24
申请人： Stephan Bradl , Olaf Heitzsch , Michael Schmidt
发明人： Stephan Bradl , Olaf Heitzsch , Michael Schmidt
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76229 , Y10S438/969
摘要： A method for forming a trench structure in a silicon substrate, which trench structure serves for electrically insulating a first region of the substrate from a second substrate region. The method proceeds from a growth of a thermal oxide layer on the substrate surface and an application and patterning of a mask layer over the thermal oxide layer. A trench of predetermined depth is subsequently etched into the silicon substrate through the patterned mask layer. The trench is filled by a deposition of a conformal covering oxide layer on the substrate with an essentially uniform thickness that is sufficient for completely filling the trench. Afterwards, a polysilicon layer is deposited on the covering oxide layer and a chemical mechanical planarization method is carried out with high selectivity S between the polysilicon material and the oxide material in order to obtain a flat surface. In a further method step, the layer is additionally removed by an essentially nonselective, joint etching of the polysilicon material and of the oxide material while maintaining a planar surface produced in the preceding planarization step. The etching operation is carried out at least until all the polysilicon material has been removed in a region of the trench.
摘要翻译：一种用于在硅衬底中形成沟槽结构的方法，该沟槽结构用于将衬底的第一区域与第二衬底区域电绝缘。该方法从衬底表面上的热氧化物层的生长和在氧化物层上的掩模层的施加和图案化开始。随后通过图案化掩模层将预定深度的沟槽蚀刻到硅衬底中。通过在衬底上沉积保形覆盖的氧化物层来填充沟槽，其厚度足以完全填充沟槽。之后，在覆盖氧化物层上沉积多晶硅层，并且在多晶硅材料和氧化物材料之间以高选择性S进行化学机械平面化方法以获得平坦表面。在另一种方法步骤中，通过基本上非选择性的多晶硅材料和氧化物材料的接合蚀刻来另外除去该层，同时保持在前面的平坦化步骤中产生的平坦表面。蚀刻操作至少直到在沟槽的区域中已经除去所有多晶硅材料为止。

9. 发明申请

US20140332937A1 WORKPIECE WITH SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A WORKPIECE WITH SEMICONDUCTOR CHIPS 审中-公开
标题翻译：具有半导体器件的半导体器件和半导体器件的制造方法以及用半导体器件制造工件的方法
公开(公告)号：US20140332937A1
公开(公告)日：2014-11-13
申请号：US14330066
申请日：2014-07-14
申请人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
发明人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
IPC分类号： H01L23/60 , H01L23/48
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/48 , H01L23/5389 , H01L23/552 , H01L23/60 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1617 , H01L2924/181 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
摘要翻译：工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

10. 发明授权

US07906860B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07906860B2
公开(公告)日：2011-03-15
申请号：US11925312
申请日：2007-10-26
申请人： Thorsten Meyer , Markus Brunnbauer , Marcus Kastner , Stephan Bradl
发明人： Thorsten Meyer , Markus Brunnbauer , Marcus Kastner , Stephan Bradl
IPC分类号： H01L23/29
CPC分类号： H01L23/5389 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/3121 , H01L23/3135 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/50 , H01L2221/68359 , H01L2224/04105 , H01L2224/20 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/12044 , H01L2924/1461 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.
摘要翻译：公开了一种半导体器件。一个实施例提供了以间隔开的关系并排布置的多个半导体芯片的布置。第一材料至少部分地填充相邻半导体芯片之间的间距。第二材料布置在半导体芯片和第一材料上。选择第一材料的热膨胀系数以使布置的横向热膨胀在与第一材料和半导体芯片相交的平面中适应布置在与第二材料相交的平面中的横向热膨胀。

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