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1. 发明申请

US20050155411A1 Method for producing a sensor or actuator arrangement, and corresponding sensor or actuator arrangement 失效
标题翻译：用于制造传感器或致动器装置的方法以及相应的传感器或致动器装置
公开(公告)号：US20050155411A1
公开(公告)日：2005-07-21
申请号：US10504738
申请日：2003-02-07
申请人： Markus Rogalla , Ingo Freund , Mirko Lehmann
发明人： Markus Rogalla , Ingo Freund , Mirko Lehmann
IPC分类号： G12B9/04 , B81B7/00 , G01N35/00 , H05K5/00 , H05K7/14 , G01N27/414
CPC分类号： B81B7/0061
摘要： In a method for producing a sensor arrangement and the resulting sensor arrangement, a sensor is provided on or in a chip and the chip is covered with a protective cover, the cover being an interface between the sensor and the environment. An adhesive layer is provided between the chip and the protective cover, the adhesive layer alone or together with the protective cover being an interface between the sensor and the environment. The protective cover and/or the adhesive layer may have a channel formed therein, the channel functioning as the reception channel for a sensor. In an alternative embodiment, the protective cover placed on a wafer with several chips, and the wafer is cut up to produce the individual chips with the protective cover. Thus, a sensor arrangement may have the protective cover applied to the individual chip after the chip is cut from the wafer, or the protective cover may be applied to the wafer, and the wafer and cover are then cut up into the individual chips and corresponding covers. The channel leading from one side of the arrangement to the sensor may be taken through the adhesive layer, through the protective cover, or through both. A hole may be formed in the protective cover above the sensor, with the sensor lying loosely in the hole. The reaction volume may be determined by the dimensions of the hole.
摘要翻译：在用于制造传感器装置和所得到的传感器装置的方法中，传感器设置在芯片上或芯片中，并且芯片被保护盖覆盖，盖是传感器和环境之间的接口。粘合剂层设置在芯片和保护盖之间，粘合剂层单独或与保护罩一起作为传感器和环境之间的界面。保护盖和/或粘合剂层可以具有形成在其中的通道，该通道用作传感器的接收通道。在替代实施例中，将保护盖放置在具有几个芯片的晶片上，并且切割晶片以用保护盖产生单独的芯片。因此，在从晶片切割芯片之后，传感器装置可以具有施加到单个芯片的保护盖，或者可以将保护盖施加到晶片，然后将晶片和盖切割成各个芯片，并且对应于盖子。从布置的一侧引导到传感器的通道可以穿过粘合剂层，通过保护盖，或者通过两者。可以在传感器上方的保护罩中形成孔，传感器松动地位于孔中。反应体积可以由孔的尺寸确定。

2. 发明授权

US07592195B2 Method for producing a sensor or actuator arrangement, and corresponding sensor or actuator arrangement 失效
标题翻译：用于制造传感器或致动器装置的方法以及相应的传感器或致动器装置
公开(公告)号：US07592195B2
公开(公告)日：2009-09-22
申请号：US10504738
申请日：2003-02-07
申请人： Markus Rogalla , Ingo Freund , Mirko Lehmann
发明人： Markus Rogalla , Ingo Freund , Mirko Lehmann
IPC分类号： H01L21/00
CPC分类号： B81B7/0061
摘要： In a method for producing a sensor arrangement and the resulting sensor arrangement, a sensor is provided on or in a chip and the chip is covered with a protective cover, the cover being an interface between the sensor and the environment. An adhesive layer is provided between the chip and the protective cover, the adhesive layer alone or together with the protective cover being an interface between the sensor and the environment. The protective cover and/or the adhesive layer may have a channel formed therein, the channel functioning as the reception channel for a sensor. In an alternative embodiment, the protective cover placed on a wafer with several chips, and the wafer is cut up to produce the individual chips with the protective cover. Thus, a sensor arrangement may have the protective cover applied to the individual chip after the chip is cut from the wafer, or the protective cover may be applied to the wafer, and the wafer and cover are then cut up into the individual chips and corresponding covers. The channel leading from one side of the arrangement to the sensor may be taken through the adhesive layer, through the protective cover, or through both. A hole may be formed in the protective cover above the sensor, with the sensor lying loosely in the hole. The reaction volume may be determined by the dimensions of the hole.
摘要翻译：在用于制造传感器装置和所得到的传感器装置的方法中，传感器设置在芯片上或芯片中，并且芯片被保护盖覆盖，盖是传感器和环境之间的接口。粘合剂层设置在芯片和保护盖之间，粘合剂层单独或与保护罩一起作为传感器和环境之间的界面。保护盖和/或粘合剂层可以具有形成在其中的通道，该通道用作传感器的接收通道。在替代实施例中，将保护盖放置在具有几个芯片的晶片上，并且切割晶片以用保护盖产生单独的芯片。因此，在从晶片切割芯片之后，传感器装置可以具有施加到单个芯片的保护盖，或者可以将保护盖施加到晶片，然后将晶片和盖切割成各个芯片，并且对应于盖子。从布置的一侧引导到传感器的通道可以穿过粘合剂层，通过保护盖，或者通过两者。可以在传感器上方的保护罩中形成孔，传感器松动地位于孔中。反应体积可以由孔的尺寸确定。

3. 发明申请

US20090153187A1 Monolithically integrated interface circuit 审中-公开
标题翻译：单片集成接口电路
公开(公告)号：US20090153187A1
公开(公告)日：2009-06-18
申请号：US10580780
申请日：2004-11-24
申请人： Reiner Bidenbach , Jörg Franke , Burkhard Giebel , Markus Rogalla
发明人： Reiner Bidenbach , Jörg Franke , Burkhard Giebel , Markus Rogalla
IPC分类号： H03K19/173
CPC分类号： G06F11/24
摘要： The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.
摘要翻译：本发明涉及包括单片集成逻辑IC的集成电路和与逻辑IC导电连接的单片集成接口电路。所述接口电路的电气特性是可编程的。接口电路的集成密度也低于逻辑IC，并且包括用于监视逻辑IC的监控模块。

4. 发明授权

US07284321B2 Method for testing a chip with a package and for mounting the package on a board 失效
标题翻译：用封装测试芯片并将封装安装在电路板上的方法
公开(公告)号：US07284321B2
公开(公告)日：2007-10-23
申请号：US11130709
申请日：2005-05-17
申请人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
发明人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
IPC分类号： H05K3/30
CPC分类号： H01L23/49555 , H01L2924/0002 , H05K13/0439 , Y10T29/49139 , Y10T29/4914 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method for testing a chip with a package having connecting pins and mounting the package on a board combines the advantages of a package with inline connecting pins with that of a package with offset connecting pins. The package with inline connecting is inserted into a socket for testing. Before mounting on the board, at least one connecting pin, preferably every second connecting pin, of the package is bent inward by a bending tool to achieve an offset arrangement of the connecting pins. The package is preferably mounted on the board using the bending tool. Since every second connecting pin is not bent inward immediately before insertion of the connecting pins, no subsequent corrective alignment of the offset connecting pins is required.
摘要翻译：用具有连接引脚的封装测试芯片的方法，并将封装安装在板上将封装的优点与具有偏置连接引脚的封装的一体式连接引脚相结合。具有内联连接的包装插入插座进行测试。在安装在板上之前，包装件的至少一个连接销（优选地每个第二连接销）由弯曲工具向内弯曲，以实现连接销的偏移布置。该包装件优选使用弯曲工具安装在板上。由于每个第二连接销在插入连接引脚之前不会向内弯曲，所以不需要随后的偏置连接引脚的校正对准。

5. 发明申请

US20060151772A1 Support device for monolithically integrated circuits 审中-公开
标题翻译：单片集成电路支持装置
公开(公告)号：US20060151772A1
公开(公告)日：2006-07-13
申请号：US10531141
申请日：2003-10-06
申请人： Giovanni Tricomi , Michael Schmidt , Wolfgang Hauser , Markus Rogalla
发明人： Giovanni Tricomi , Michael Schmidt , Wolfgang Hauser , Markus Rogalla
IPC分类号： H01L47/02
CPC分类号： H01L24/49 , H01L23/49503 , H01L24/45 , H01L24/48 , H01L2224/05599 , H01L2224/45144 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00015 , H01L2224/45015 , H01L2924/207
摘要： A carrier device for a monolithic integrated circuit has portions for the connection of bonding wires in the form of pedestals that rise above a chip connection area on the carrier device and have steep sides.
摘要翻译：用于单片集成电路的载体装置具有用于连接在载体装置上上升到芯片连接区域上方并具有陡峭侧面的基座形式的接合线的部分。

6. 发明授权

US07053480B2 Integrated circuit with offset pins 有权
标题翻译：带偏置引脚的集成电路
公开(公告)号：US07053480B2
公开(公告)日：2006-05-30
申请号：US10485139
申请日：2002-07-26
申请人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
发明人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
IPC分类号： H01L23/48
CPC分类号： H01L23/49555 , H01L2924/0002 , H05K13/0439 , Y10T29/49139 , Y10T29/4914 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means. Since every second connecting pin (12) is not bent inward immediately before insertion of the connecting pins (11,12), no subsequent corrective alignment of the offset connecting pins (11, 12) is required.
摘要翻译：本发明涉及具有连接销（1）的封装（2）以及将封装（2）安装在板（5）上的芯片的制造和测试，从而为了将封装（2）具有带有偏置连接销（11,12）的封装（2）的优点的带有内联连接引脚（1）的封装（2）由线内连接引脚（1）制成并插入测试插座 3）进行测试。在安装在板（5）上之前，封装（2）的至少一个连接销（优选地每个第二连接销（12））由弯曲工具（6）向内弯曲，以实现连接销（11,12）。包装（2）优选使用弯曲工具（6）安装在板（5）上。一个简单，廉价的测试插座（3）足以用于测试芯片。廉价生产的引导支架（4）例如适合作为包装装置。由于每个第二连接销（12）在插入连接销（11,12）之前不向内弯曲，所以不需要随后的偏置连接销（11,12）的校正对准。

7. 发明申请

US20050258849A1 Method for testing a chip with a package and for mounting the package on a board 失效
标题翻译：用封装测试芯片并将封装安装在电路板上的方法
公开(公告)号：US20050258849A1
公开(公告)日：2005-11-24
申请号：US11130709
申请日：2005-05-17
申请人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
发明人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
IPC分类号： H05K13/04 , G01R31/02
CPC分类号： H01L23/49555 , H01L2924/0002 , H05K13/0439 , Y10T29/49139 , Y10T29/4914 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means. Since every second connecting pin (12) is not bent inward immediately before insertion of the connecting pins (11, 12), no subsequent corrective alignment of the offset connecting pins (11, 12) is required.
摘要翻译：本发明涉及具有连接销（1）的封装（2）以及将封装（2）安装在板（5）上的芯片的制造和测试，从而为了将封装（2）具有带有偏置连接销（11,12）的封装（2）的优点的带有内联连接引脚（1）的封装（2）由线内连接引脚（1）制成并插入测试插座 3）进行测试。在安装在板（5）上之前，封装（2）的至少一个连接销（优选地每个第二连接销（12））由弯曲工具（6）向内弯曲，以实现连接销（11,12）。包装（2）优选使用弯曲工具（6）安装在板（5）上。一个简单，廉价的测试插座（3）足以用于测试芯片。廉价生产的引导支架（4）例如适合作为包装装置。由于每个第二连接销（12）在插入连接销（11,12）之前不向内弯曲，所以不需要随后的偏移连接销（11,12）的校正对准。

8. 发明授权

US06964927B2 Method and production of a sensor 失效
标题翻译：传感器的方法和生产
公开(公告)号：US06964927B2
公开(公告)日：2005-11-15
申请号：US10149560
申请日：2001-12-07
申请人： Günter Igel , Markus Rogalla
发明人： Günter Igel , Markus Rogalla
IPC分类号： H01L21/56 , H01L31/0203 , H01L31/0232 , H01L21/302
CPC分类号： H01L31/0203 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for producing a sensor (1), wherein a carrier chip (2) is produced. Said chip is provided with a sensor structure (3) comprising an active sensor surface (4). A material (9) capable of flowing is applied onto carrier chips (2) in such a way that the sensor structure (3) has a thinner layer thickness on said active sensor surface (4) than on the area of the carrier chip (2) which borders on the active sensor surface (4). The material (9) which is capable of flowing is hardened thereafter. The hardened material (9) is subsequently removed by chemical means from the surface which faces said carrier chip (2) until the active sensor surface of the sensor structure is layed bare.
摘要翻译：本发明涉及一种制造传感器（1）的方法，其中制造了载体芯片（2）。所述芯片设置有包括有源传感器表面（4）的传感器结构（3）。将能够流动的材料（9）施加到载体芯片（2）上，使得传感器结构（3）在所述主动传感器表面（4）上具有比载体芯片（2）的区域更薄的层厚度），其接合在主动传感器表面（4）上。能够流动的材料（9）之后被硬化。随后通过化学方法从面向所述载体芯片（2）的表面去除硬化材料（9），直到传感器结构的有源传感器表面裸露。

9. 发明授权

US07414308B2 Integrated circuit with offset pins 失效
标题翻译：带偏置引脚的集成电路
公开(公告)号：US07414308B2
公开(公告)日：2008-08-19
申请号：US11297047
申请日：2005-12-07
申请人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
发明人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
IPC分类号： H01L23/48
CPC分类号： H01L23/49555 , H01L2924/0002 , H05K13/0439 , Y10T29/49139 , Y10T29/4914 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An integrated circuit comprises a package and having adjacent connection pins on two opposite sides of the package, with every second connection pin being inwardly bent so that the connection pins are offset. The ends of the inwardly bent connection pins and the ends of the outer connection pins each lie on a straight line, where the offset connection pins are bent by different angles out of the plane of the package.
摘要翻译：集成电路包括封装并且在封装的两个相对侧上具有相邻的连接引脚，每个第二连接引脚被向内弯曲，使得连接引脚被偏移。向内弯曲的连接销的端部和外部连接销的端部各自位于直线上，其中偏移连接销以不同的角度弯曲离开包装的平面。

10. 发明申请

US20060108679A1 Method for testing a chip with a package and for mounting the package on a board 失效
标题翻译：用封装测试芯片并将封装安装在电路板上的方法
公开(公告)号：US20060108679A1
公开(公告)日：2006-05-25
申请号：US11297047
申请日：2005-12-07
申请人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
发明人： Wolfgang Hauser , Heiko Dreher , Christian Kimstedt , Markus Rogalla
IPC分类号： H01L23/48
CPC分类号： H01L23/49555 , H01L2924/0002 , H05K13/0439 , Y10T29/49139 , Y10T29/4914 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： The invention relates to the fabrication and testing of a chip with a package (2) having connecting pins (1) as well as to mounting the package (2) on a board (5), whereby in order to combine the advantages of a package (2) with inline connecting pins (1) with the advantages of a package (2) with offset connecting pins (11, 12), the package (2) is fabricated with inline connecting pins (1) and inserted into a test socket (3) for testing. Immediately before mounting on the board (5), at least one connecting pin, preferably every second connecting pin (12), of the package (2) is bent inward by a bending tool (6) so as to achieve an offset arrangement of the connecting pins (11, 12). The package (2) is preferably mounted on the board (5) using the bending tool (6). A simple, inexpensively produced test socket (3) is sufficient for the purpose of testing the chip. An inexpensively produced guide brace (4), for example, is suitable as a packaging means. Since every second connecting pin (12) is not bent inward immediately before insertion of the connecting pins (11, 12), no subsequent corrective alignment of the offset connecting pins (11, 12) is required.
摘要翻译：本发明涉及具有连接销（1）的封装（2）以及将封装（2）安装在板（5）上的芯片的制造和测试，从而为了将封装（2）具有带有偏置连接销（11,12）的封装（2）的优点的带有内联连接引脚（1）的封装（2）由线内连接引脚（1）制成并插入测试插座 3）进行测试。在安装在板（5）上之前，封装（2）的至少一个连接销（优选地每个第二连接销（12））由弯曲工具（6）向内弯曲，以实现连接销（11,12）。包装（2）优选使用弯曲工具（6）安装在板（5）上。一个简单，廉价的测试插座（3）足以用于测试芯片。廉价生产的引导支架（4）例如适合作为包装装置。由于每个第二连接销（12）在插入连接销（11,12）之前不向内弯曲，所以不需要随后的偏移连接销（11,12）的校正对准。

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