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1. 发明授权

US07293120B2 DMA module having plurality of first addressable locations and determining if first addressable locations are associated with originating DMA process 有权
标题翻译： DMA模块具有多个第一可寻址位置并且确定第一可寻址位置是否与始发DMA进程相关联
公开(公告)号：US07293120B2
公开(公告)日：2007-11-06
申请号：US10751668
申请日：2004-01-05
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/28
摘要： A DMA module includes an address generator to perform a write or read access to a location of an addressable memory, and an address counter to advance a stored address to an adjacent memory location. The address counter does not act on an internal register of the DMA module but instead is configured so that between reading an address value from the memory and writing the address value to the memory, the address counter is advanced once. The memory location at which the address value is read or written takes on the function of a register conventionally integrated in the DMA module. This approach reduces the space requirement of the DMA module, and the DMA module may be employed to control a large number of DMA processes that may mutually interrupt each other by providing a plurality of memory locations to store specifications of the DMA blocks.
摘要翻译： DMA模块包括地址发生器，用于执行对可寻址存储器的位置的写入或读取访问，以及地址计数器，用于将存储的地址推进到相邻存储器位置。地址计数器不对DMA模块的内部寄存器起作用，而是配置为在从存储器读取地址值并将地址值写入存储器之前，地址计数器被提前一次。读取或写入地址值的存储器位置具有常规集成在DMA模块中的寄存器的功能。这种方法减少了DMA模块的空间需求，并且可以采用DMA模块来控制可以通过提供多个存储器位置来存储DMA块的规范来相互中断的大量DMA进程。

2. 发明授权

US5326994A Protective circuit for protecting contacts of monolithic integrated circuits by preventing parasitic latch up with other integrated circuit elements 失效
标题翻译：用于通过防止与其他集成电路元件的寄生锁存来保护单片集成电路的触点的保护电路
公开(公告)号：US5326994A
公开(公告)日：1994-07-05
申请号：US955765
申请日：1992-10-02
申请人： Burkhard Giebel , Wilfried W. Gehrig
发明人： Burkhard Giebel , Wilfried W. Gehrig
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L29/74 , H01L29/06 , H01L29/78
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).
摘要翻译：用于连接单片集成电路的触点的保护电路，特别是CMOS输入/输出级。保护电路具有在每个连接触点（A）的区域中具有确定的开关阈值的四层器件（ta，ts）和从连接触点（A）到电源端子的低电阻率电流通路（sa）（VSS，VDD）。保护电路还包含用于在四层器件和可触发电路区域（W2）的至少部分之间防止或提供任何不期望的电流（i3，i4）的旁路的器件（zw2，z5）。

3. 发明授权

US4750158A Integrated matrix of nonvolatile, reprogrammable storage cells 失效
标题翻译：非易失性，可编程存储单元的集成矩阵
公开(公告)号：US4750158A
公开(公告)日：1988-06-07
申请号：US461791
申请日：1983-01-28
申请人： Burkhard Giebel , Thomas Fischer
发明人： Burkhard Giebel , Thomas Fischer
IPC分类号： G06F12/16 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/76 , G11C29/789 , G11C29/822
摘要： In an integrated matrix of nonvolatile, reprogrammable storage cells, additional memory is provided to replace defective rows of storage cells. The addresses of the defective rows are stored in a region of the matrix. A correction register can be loaded with the addresses of the defective rows from the region of the matrix when power is first applied to the matrix or whenever the applied power deviates from the expected, nominal value.
摘要翻译：在非易失性可再编程存储单元的集成矩阵中，提供了附加存储器来代替存储单元的有缺陷的行。有缺陷的行的地址存储在矩阵的区域中。当功率首次施加到矩阵时或每当施加的功率偏离预期的标称值时，校正寄存器可以从矩阵的区域加载有缺陷行的地址。

4. 发明授权

US4597064A Electrically programmable memory matrix 失效
标题翻译：电可编程存储矩阵
公开(公告)号：US4597064A
公开(公告)日：1986-06-24
申请号：US518239
申请日：1983-07-28
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： G11C17/00 , G11C7/00 , G11C16/02 , G11C16/08 , G11C16/10 , G11C8/00
CPC分类号： G11C16/08 , G11C16/10
摘要： An electrically programmable memory matrix comprises electrically programmable memory cells arranged in columns and rows, each consisting of a source-drain series arrangement of a memory transistor with a select transistor. The gate of the select transistor may be connected to one of row selecting lines of a row decoder, to which there are connected all gates of one row of the selected transistors of the memory cells of the same row. Control gates of groups of memory transistors (Ts) of one row may be connected to one common programming line, with these programming lines being connected by blocks via each time one group select transistor to one common block line which, via the source-drain line of a block select transistor whose gate is connected to one of a plurality of outputs of a block decoder is connected to one source of block signals. Re-programmability of a fixed number of memory cells only upon application of a further input signal, apart from a function signal, is accomplished by subdividing at least one of the two decoders into a first decoder part to the function signal input of which the programming signal is applied directly, and into a second decoder part whose function signal input is connected to the output of a gate circuit having two inputs. Th output signal of the gate circuit is only then at the value corresponding to the function "programming" when the first input is also at the value corresponding to the function "programming", and when the second input is at that particular value which permits a programming of the second decoder part.
摘要翻译：电可编程存储器矩阵包括以列和行排列的电可编程存储单元，每一个由具有选择晶体管的存储晶体管的源 - 漏串联布置组成。选择晶体管的栅极可以连接到行解码器的行选择线之一，其中连接同一行的存储器单元的所选晶体管的一行的所有栅极。一行的存储晶体管（Ts）的组的控制栅极可以连接到一个公共编程线，这些编程线通过每个一个组选择晶体管通过块连接到一个公共块线，其经由源极 - 漏极线其栅极连接到块解码器的多个输出中的一个的块选择晶体管连接到块信号的一个源。除了功能信号之外，仅在施加另外的输入信号时，固定数量的存储器单元的可重新编程通过将两个解码器中的至少一个分解为第一解码器部分来实现，该第一解码器部分编程为功能信号输入信号直接施加到第二解码器部分，其功能信号输入连接到具有两个输入的门电路的输出。当第一输入也处于与功能“编程”相对应的值时，门电路的Th输出信号仅处于对应于功能“编程”的值，并且当第二输入处于允许第二解码器部分的编程。

5. 发明授权

US4527256A Electrically erasable memory matrix (EEPROM) 失效
标题翻译：电可擦除存储矩阵（EEPROM）
公开(公告)号：US4527256A
公开(公告)日：1985-07-02
申请号：US470759
申请日：1983-02-28
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： G11C29/00 , G11C11/34 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/24 , G11C17/00 , G11C29/04 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/24
摘要： EEPROM showing storage cells comprising a tunnel injector which at the one hand is connected to a first bit line by means of the source-drain-line of a floating gate FET and at the other hand to a second bit line by means of the source-drain-line of a selection FET. Interferences between addressed groups and not addressed groups of storage cells during writing are eliminated by means of connection of the first bitline of the not addressed groups via the source-drain-lines of a depletion type FET and an enhancement FET to ground.
摘要翻译： EEPROM显示包括隧道注射器的存储单元，其一方面通过浮置栅极FET的源极 - 漏极线连接到第一位线，另一方面通过源极 - 漏极连接到第二位线，选择FET的漏极线。借助于经由耗尽型FET和增强型FET的源极 - 漏极到地的非寻址组的第一位线的连接来消除写入期间寻址组和未寻址组的存储单元之间的干扰。

6. 发明授权

US4524429A Integrated memory matrix comprising nonvolatile reprogrammable storage cells 失效
标题翻译：包括非易失性可再编程存储单元的集成存储器矩阵
公开(公告)号：US4524429A
公开(公告)日：1985-06-18
申请号：US472349
申请日：1983-03-04
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/12 , G11C29/50 , G11C11/40
CPC分类号： G11C29/50 , G11C16/0433 , G06F2201/81 , G11C16/04
摘要： The invention discloses an integrated memory matrix comprising nonvolatile reprogrammable storage (memory) cells arranged in rows and columns, as well as a classifying circuit integrated as well in the semiconductor body of the memory matrix, containing a nonprogrammable reference storage cell (Mr) of the same construction as that of the storage cells, and which is manufactured simultaneously as a comparison standard, with the storage cells. With the aid of a first voltage divider (Q1) integrated as well, whose output voltage is adjustable in steps, and whose output current is fed into the source-drain line of the reference storage cell (Mr) and/or of a second voltage divider (Q2) adjustable in steps and integrated as well, whose output voltage is applied to the control gate of the storage transistor (Ts) of the reference storage cell (Mr), it is possible to simulate a threshold voltage which is compared with the threshold voltages of the storage cells (M11 . . . Mmn) of the memory matrix (S) either individually or in groups with the aid of a comparator circuit (Ad) for obtaining a classifying criterion.
摘要翻译：本发明公开了一种集成存储器矩阵，其包括排列成行和列的非易失性可再编程存储（存储器）单元，以及集成在存储器矩阵的半导体本体中的分类电路，其包含不可编程的参考存储单元与存储单元的构造相同，并且作为比较标准与存储单元同时制造。借助于集成的第一分压器（Q1），其输出电压可以步进地调节，并且其输出电流被馈送到参考存储单元（Mr）的源极 - 漏极线和/或第二电压分压器（Q2）可以步进调节并集成，其输出电压施加到参考存储单元（Mr）的存储晶体管（Ts）的控制栅极，可以模拟与借助于用于获得分类标准的比较器电路（Ad），单独地或分组地存储矩阵（S）的存储单元（M11 ... Mmn）的阈值电压。

7. 发明授权

US5608346A MOS driver circuit for suppressing interference by preventing shunt currents 失效
标题翻译： MOS驱动电路，用于通过防止分流电流来抑制干扰
公开(公告)号：US5608346A
公开(公告)日：1997-03-04
申请号：US491500
申请日：1995-06-16
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： H03K19/00 , H03K17/16
CPC分类号： H03K19/0013
摘要： A MOS driver circuit has a first output transistor and a second output transistor which are driven in push-pull into a conducting state by a first driver stage having first high impedance and first low impedance elements and a second driver stage having second high impedance and second low impedance elements, respectively. The high impedance driver elements drive the output transistors into a conducting or nonconducting state and the low impedance driver elements hold the output transistors in the nonconducting state. The junction of the output transistors can be connected to a load. A holding stage for each driver stage is cross coupled to a high impedance driver element of one output transistor and the low impedance driver element of the other output transistor, so as to drive one output transistor in the conducting state while holding the other output transistor in a nonconducting state. As a result, shunt currents between the output transistors are avoided even in the presence of output noise.
摘要翻译： MOS驱动器电路具有第一输出晶体管和第二输出晶体管，所述第一输出晶体管和第二输出晶体管通过具有第一高阻抗和第一低阻抗元件的第一驱动级被推挽驱动而导通状态，以及具有第二高阻抗和第二高阻抗元件的第二驱动级低阻抗元件。高阻抗驱动器元件将输出晶体管驱动成导通或不导通状态，并且低阻抗驱动器元件将输出晶体管保持在非导通状态。输出晶体管的结可以连接到负载。每个驱动级的保持级与一个输出晶体管的高阻抗驱动器元件和另一个输出晶体管的低阻抗驱动元件交叉耦合，以便将一个输出晶体管驱动在导通状态，同时将另一个输出晶体管保持在非导体状态。结果，即使在存在输出噪声的情况下也避免了输出晶体管之间的分流电流。

8. 发明授权

US4502131A Electrically programmable memory matrix 失效
标题翻译：电可编程存储矩阵
公开(公告)号：US4502131A
公开(公告)日：1985-02-26
申请号：US530528
申请日：1983-09-09
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： G11C29/00 , G11C29/34
CPC分类号： G11C29/34
摘要： An electrically programmable memory includes a test circuit usable for detection of interaction between adjacent memory cells by easily permitting a checkerboard-pattern to be programmed into the memory.
摘要翻译：电可编程存储器包括可用于通过容易地将棋盘图形编程到存储器中来检测相邻存储器单元之间的相互作用的测试电路。

9. 发明授权

US4458338A Circuit for checking memory cells of programmable MOS-integrated semiconductor memories 失效
标题翻译：用于检查可编程MOS集成半导体存储器的存储单元的电路
公开(公告)号：US4458338A
公开(公告)日：1984-07-03
申请号：US290514
申请日：1981-08-06
申请人： Burkhard Giebel , Hans Moormann , Lothar Schrader
发明人： Burkhard Giebel , Hans Moormann , Lothar Schrader
IPC分类号： G01R31/26 , G06F12/16 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/46 , G11C7/00
CPC分类号： G11C29/46 , G11C29/34
摘要： Circuit arrangement for checking memory cells of programmable MOS-integrated semiconductor memories, especially non-volatile semiconductor memories of the floating-gate type, has an active programming and read mode of operation wherein all word lines of the semiconductor memory with the exception of one selected word line are at a low level. The circuit arrangement also has an inactive power-down mode of operation, wherein all word lines at a high level. Both of the modes of operation are represented by a signal having a first level for the active mode of operation and a second level for the inactive mode of operation. The circuit arrangement further includes a single circuit in the semiconductor memory switchable via a first signal indicating the operating mode for the memory cell test, wherein all of the word lines are addressed by a voltage corresponding to the programming voltage, as a function of a single second signal fed into the semiconductor memory from the outside, from the level indicating the active mode of operation to the level indicating the inactive mode of operation, so that all the word lines can be switched simultaneously to the level required for programming.
摘要翻译：用于检查可编程MOS集成半导体存储器，特别是浮栅型非易失性半导体存储器的存储单元的电路布置具有有效的编程和读操作模式，其中半导体存储器的所有字线除了一个选定的字线处于低水平。电路装置还具有无效的掉电操作模式，其中所有字线处于高电平。这两种操作模式由具有用于主动操作模式的第一级的信号和用于非活动操作模式的第二级来表示。该电路装置还包括半导体存储器中的单个电路，其经由指示存储器单元测试的工作模式的第一信号可转换，其中所有字线由与编程电压相对应的电压作为单个电路的函数第二信号从外部馈送到半导体存储器，从指示活动操作模式的电平到指示不活动操作模式的电平，使得所有字线可以同时切换到编程所需的电平。

10. 发明授权

US4388541A Circuit arrangement with MOS-transistors for the rapid evaluation of the logic state of a sampling node 失效
标题翻译：具有MOS晶体管的电路布置，用于快速评估采样节点的逻辑状态
公开(公告)号：US4388541A
公开(公告)日：1983-06-14
申请号：US171342
申请日：1980-07-23
申请人： Burkhard Giebel
发明人： Burkhard Giebel
IPC分类号： G11C17/00 , G11C11/4063 , G11C16/26 , G11C17/18 , H03K19/017 , H03K19/0175 , H03K5/12 , H03K19/094
CPC分类号： H03K19/01721 , G11C11/4063 , G11C16/26
摘要： Circuit having MOS-transistors for the rapid evaluation of the logic state of a sampling node, including a circuit input connected to the sampling node, a circuit output, a supply voltage source, an inverter being connected to the circuit input and having an output, a first transistor being connected between the circuit input and the circuit output and having a gate connected to the output of the inverter, a second transistor being connected between the supply voltage source and the circuit output and having a gate connected to the output of the inverter, and a third transistor shunted across the second transistor as a load resistor.
摘要翻译：具有用于快速评估采样节点的逻辑状态的MOS晶体管的电路，包括连接到采样节点的电路输入，电路输出，电源电压源，连接到电路输入并具有输出的反相器，第一晶体管连接在电路输入端和电路输出端之间，并具有连接到反相器的输出端的栅极，第二晶体管连接在电源电压源和电路输出端之间，并具有连接到反相器的输出端的栅极并且作为负载电阻器将分流在第二晶体管上的第三晶体管分流。

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