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1. 发明授权

US5555387A Method and apparatus for implementing virtual memory having multiple selected page sizes 失效
标题翻译：用于实现具有多个所选页面大小的虚拟存储器的方法和装置
公开(公告)号：US5555387A
公开(公告)日：1996-09-10
申请号：US467266
申请日：1995-06-06
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Kevin G. Plotz , Fadi-Christian E. Safi , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Kevin G. Plotz , Fadi-Christian E. Safi , Albert A. Slane
IPC分类号： G06F12/02 , G06F12/10 , G11B25/04 , G11B33/12 , G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/10 , G06F12/1009 , G11B25/043 , G06F12/0292 , G06F2212/652 , G11B33/12
摘要： A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.
摘要翻译：提供一种用于实现具有多个选定页面大小的虚拟存储器的方法和装置。虚拟地址包括地图索引和帧偏移量。选择器机构接收虚拟地址帧偏移并生成偏移量和索引。帧映射表索引虚拟地址映射索引和选择器生成的索引，并生成基址。帧映射表生成的基地址和选择器生成的偏移量被组合以提供物理地址。

2. 发明授权

US5533021A Apparatus and method for segmentation and time synchronization of the transmission of multimedia data 失效
标题翻译：多媒体数据传输的分段和时间同步的装置和方法
公开(公告)号：US5533021A
公开(公告)日：1996-07-02
申请号：US382905
申请日：1995-02-03
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
IPC分类号： H04N7/26 , G06F17/30 , G06F19/00 , H04J3/06 , H04L12/56 , H04L29/06 , H04L29/08 , H04N7/24 , H04N7/52 , H04N21/2343 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/43 , H04N21/434 , H04N21/4363 , H04N21/438 , H04N21/472 , H04N21/643 , H04N21/845 , H04N21/8547 , H04Q3/00 , H04Q11/04 , H04N7/62
CPC分类号： H04Q11/0478 , H04L29/06 , H04L65/607 , H04N21/234318 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/26208 , H04N21/4307 , H04N21/4341 , H04N21/4363 , H04N21/4381 , H04N21/47202 , H04N21/64307 , H04N21/8456 , H04N21/8547 , H04J3/0632 , H04L2012/5616 , H04L2012/565 , H04L2012/5652 , H04L2012/5664 , H04L2012/5674 , H04L2012/5679 , H04L29/06027 , H04L69/324 , H04L69/326
摘要： Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.
摘要翻译：提供了用于通过分发通信网络发送多媒体数字数据流的方法和装置。多媒体流服务器将多媒体数字数据流分割成第一边界和第二边界上的数据块。第一边界是一组传输系统数据分组，第二边界是包括时间戳的传输系统数据分组。调度器调度分段数据块进行传输。多媒体流服务器解码分段的数据块以定位时间戳，并将所定位的时间戳数据块的传输与由时间戳指示的时间值进行匹配。可以在连接建立时确定传送系统数据包的设定数量，而不是所有会话的预定值。在接收机处，可以提供接收到的多媒体数据的批量处理。

3. 发明授权

US5537408A apparatus and method for segmentation and time synchronization of the transmission of multimedia data 失效
标题翻译：多媒体数据传输的分段和时间同步的装置和方法
公开(公告)号：US5537408A
公开(公告)日：1996-07-16
申请号：US463207
申请日：1995-06-05
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Phillip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Phillip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
IPC分类号： H04N7/26 , G06F17/30 , G06F19/00 , H04J3/06 , H04L12/56 , H04L29/06 , H04L29/08 , H04N7/24 , H04N7/52 , H04N21/2343 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/43 , H04N21/434 , H04N21/4363 , H04N21/438 , H04N21/472 , H04N21/643 , H04N21/845 , H04N21/8547 , H04Q3/00 , H04Q11/04 , H04N5/04
CPC分类号： H04Q11/0478 , H04L29/06 , H04L65/607 , H04N21/234318 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/26208 , H04N21/4307 , H04N21/4341 , H04N21/4363 , H04N21/4381 , H04N21/47202 , H04N21/64307 , H04N21/8456 , H04N21/8547 , H04J3/0632 , H04L2012/5616 , H04L2012/565 , H04L2012/5652 , H04L2012/5664 , H04L2012/5674 , H04L2012/5679 , H04L29/06027 , H04L69/324 , H04L69/326
摘要： Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.
摘要翻译：提供了用于通过分发通信网络发送多媒体数字数据流的方法和装置。多媒体流服务器将多媒体数字数据流分割成第一边界和第二边界上的数据块。第一边界是一组传输系统数据分组，第二边界是包括时间戳的传输系统数据分组。调度器调度分段数据块进行传输。多媒体流服务器解码分段的数据块以定位时间戳，并将所定位的时间戳数据块的传输与由时间戳指示的时间值进行匹配。可以在连接建立时确定传送系统数据包的设定数量，而不是所有会话的预定值。在接收机处，可以提供接收到的多媒体数据的批量处理。

4. 发明授权

US5737638A System for determining plurality of data transformations to be performed upon single set of data during single transfer by examining communication data structure 失效
标题翻译：用于通过检查通信数据结构来确定在单次传送期间对单个数据集合执行的多个数据变换的系统
公开(公告)号：US5737638A
公开(公告)日：1998-04-07
申请号：US502782
申请日：1995-07-14
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Robert J. Manulik , Arthur J. Meyer, III , Albert A. Slane
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Robert J. Manulik , Arthur J. Meyer, III , Albert A. Slane
IPC分类号： G06F13/40 , G06F3/00 , G06F15/16
CPC分类号： G06F13/4027
摘要： A method and apparatus are disclosed for providing an inline data service within a data processing system coupled to a communications network. The data processing system includes a host memory. According to the present invention, the apparatus comprises an adapter memory for temporarily storing data communicated between the data processing system and the communications network and a memory access controller, which controls transfers of data between the adapter memory and the host memory. The apparatus further includes means for selectively performing a data transformation on data transferred between the adapter memory and the host memory, wherein the data transformation is performed during a transfer of the data such that data communication latency is reduced. In a second preferred embodiment of the present invention, a multibus data processing system has a processor and a first memory coupled to a first bus and a second memory coupled to a second bus. A bridge adapter, including means for transferring data from the first memory to the second memory and means for selectively performing a data transformation, is coupled between the first and second buses. During transfers of data from the first memory to the second memory, the bridge adapter selectively performs data transformations on the data, such that data processing latency is reduced.
摘要翻译：公开了用于在耦合到通信网络的数据处理系统内提供在线数据服务的方法和装置。数据处理系统包括主机存储器。根据本发明，该装置包括用于临时存储在数据处理系统和通信网络之间传送的数据的适配器存储器和控制适配器存储器和主机存储器之间的数据传输的存储器访问控制器。该装置还包括用于选择性地对在适配器存储器和主机存储器之间传送的数据执行数据变换的装置，其中在数据传送期间执行数据变换，使得数据通信等待时间减少。在本发明的第二优选实施例中，多位数据处理系统具有耦合到第一总线的处理器和第一存储器，以及耦合到第二总线的第二存储器。包括用于将数据从第一存储器传送到第二存储器的装置和用于选择性地执行数据变换的装置的桥接器耦合在第一和第二总线之间。在从第一存储器传输到第二存储器的数据传输期间，桥接器适配器有选择地对数据进行数据转换，从而减少数据处理等待时间。

5. 发明授权

US5533020A ATM cell scheduler 失效
标题翻译： ATM信元调度器
公开(公告)号：US5533020A
公开(公告)日：1996-07-02
申请号：US332160
申请日：1994-10-31
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Baiju V. Patel , Kevin G. Plotz , Frank A. Schaffa , Marc H. Willebeek-LeMair
IPC分类号： G06F13/00 , H04L12/56 , H04L29/06 , H04L29/08 , H04Q3/00 , H04Q11/04
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5635 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679
摘要： A method and apparatus for scheduling the transmission of a number of data streams over a common communications link, where each of the data streams conforms to a corresponding set of flow control parameters. Each of the data streams to be transmitted on the communications link is stored in a corresponding queue. The status of each queue is maintained, and a target transmission time is calculated for each queue. Signals are then generated for each queue at a time at least after the target transmission time, and these signals are used to indicate to a corresponding queue that is can transmit a cell on the link. Upon reception of a corresponding signal, a queue then transmits at least one cell onto the communications link.
摘要翻译：一种用于通过公共通信链路调度多个数据流的传输的方法和装置，其中每个数据流符合对应的一组流量控制参数。要在通信链路上发送的每个数据流都存储在相应的队列中。维护每个队列的状态，并计算每个队列的目标传输时间。然后至少在目标传输时间之后，每个队列生成信号，并且这些信号用于指示可以在链路上传送单元的相应队列。在接收到对应信号时，队列随后将至少一个小区发送到通信链路上。

6. 发明授权

US5260942A Method and apparatus for batching the receipt of data packets 失效
标题翻译：批量接收数据包的方法和装置
公开(公告)号：US5260942A
公开(公告)日：1993-11-09
申请号：US847470
申请日：1992-03-06
申请人： Richard A. Auerbach , Jerry A. Blades , Jonathan W. Byrn , Gary S. Delp
发明人： Richard A. Auerbach , Jerry A. Blades , Jonathan W. Byrn , Gary S. Delp
IPC分类号： H04L12/56 , H04L29/06 , H04J3/14
CPC分类号： H04L12/56 , H04L29/06 , H04L69/22
摘要： A method and a system in a distributed data processing network for enhancing the processing of a plurality of related data packets received at a receiving station within the distributed data processing network, each of the data packets having a header associated herewith includes sequentially receiving a number of data packets at the receiving station. Next, the header associated with a first data packet is examined and predicted profile is generated for comparison with a related subsequent data packet. The next data packet received is then compared with the predicted profile to determine whether or not the two data packets may be consolidated.

7. 发明授权

US5502833A System and method for management of a predictive split cache for supporting FIFO queues 失效
标题翻译：用于管理用于支持FIFO队列的预测分裂高速缓存的系统和方法
公开(公告)号：US5502833A
公开(公告)日：1996-03-26
申请号：US221140
申请日：1994-03-30
申请人： Jonathan W. Byrn , Gary S. Delp
发明人： Jonathan W. Byrn , Gary S. Delp
IPC分类号： G06F5/06 , G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F5/06 , G06F12/0875
摘要： A first-in, first-out queue is implemented on two memory elements by enqueuing and dequeuing items from a first memory element and by swapping middle portions of the queue between the first memory element and the second memory whenever the first memory element is sufficiently filled. Where the second element is system memory for a computer system, queue length can be allowed to grow almost arbitrarily while preserving the performance of first memory element.
摘要翻译：通过对来自第一存储器元件的项进行排队和排队，并且每当第一存储器元件被充分填充时，将队列的中间部分交换在第一存储器元件和第二存储器之间，在两个存储器元件上实现先入先出队列。在第二个元素是计算机系统的系统存储器的情况下，可以允许队列长度几乎任意增长，同时保持第一个存储器元件的性能。

8. 发明授权

US08196086B2 Granular channel width for power optimization 有权
标题翻译：颗粒通道宽度进行功率优化
公开(公告)号：US08196086B2
公开(公告)日：2012-06-05
申请号：US12840535
申请日：2010-07-21
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/78
摘要： A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.
摘要翻译：记录具有一个或多个可由计算机读取的单元的单元库的存储介质，并可由计算机用于设计集成电路。一个或多个单元可以具有物理尺寸参数和通道宽度参数。物理尺寸参数可以是一个或多个单元格的占位面积。通道宽度参数可能具有最小驱动程序大小和最大驱动程序大小。通道宽度参数可以定义范围，在该范围内，工具在集成电路的设计流程期间基于一个或多个功率准则改变最大驱动器尺寸和最小驱动器尺寸之间的通道宽度，而不改变占用面积。

9. 发明授权

US07966592B2 Dual path static timing analysis 有权
标题翻译：双路静态时序分析
公开(公告)号：US07966592B2
公开(公告)日：2011-06-21
申请号：US12206048
申请日：2008-09-08
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method to analyze timing in a circuit, generally including (A) simulating reception of an input signal and a clock signal at a first flip-flop, wherein (i) the input signal has a latest transition, (ii) the input signal arrives through a first path and (iii) the clock signal has an active edge, (B) calculating a value of a time difference between the latest transition and the active edge, (C) calculating a delay between the active edge and the latest transition appearing in an output signal, wherein (i) the delay is based on a model responding to the value, (ii) the model characterizes a clock-to-output delay as a function of the time difference and (iii) the characterization covering a range of values, (D) calculating an arrival time of the latest transition at a second flip-flop through a second signal path and (E) storing the arrival time in a recording medium.
摘要翻译：一种分析电路中的定时的方法，通常包括（A）模拟第一触发器处的输入信号和时钟信号的接收，其中（i）输入信号具有最新的转换，（ii）输入信号到达通过第一路径和（iii）时钟信号具有有效边缘，（B）计算最新转换和有效边沿之间的时间差值，（C）计算出当前边缘与最近转换出现之间的延迟在输出信号中，其中（i）所述延迟基于响应于该值的模型，（ii）模型将时钟到输出延迟表征为时间差的函数，以及（iii）表征范围（D）通过第二信号路径计算第二触发器的最新转换的到达时间，以及（E）将到达时间存储在记录介质中。

10. 发明授权

US07787325B2 Row decode driver gradient design in a memory device 有权
标题翻译：行解码驱动程序渐变设计在内存设备中
公开(公告)号：US07787325B2
公开(公告)日：2010-08-31
申请号：US12120611
申请日：2008-05-14
申请人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
发明人： Jeffrey S. Brown , Jonathan W. Byrn , Mark F. Turner
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals.
摘要翻译：公开了一种使用多个用于激活存储器阵列中的字线的增强行解码驱动器的存储器件。增强行解码驱动器的电路设计属性作为与施加到每个解码驱动器的行地址信号的源的接近度的函数而变化。电路变化可操作以通过降低其性能而降低驾驶员的泄漏功率，同时保持所需的最差情况时机。最差的情况定时由相对于应用的行地址信号的源的最远的行解码驱动器电路的定时和性能要求定义。

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