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1. 发明授权

US07543204B2 Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree 失效
标题翻译：用于设计用于匹配时钟树门控部分的逻辑扫描链的方法，装置和计算机程序产品
公开(公告)号：US07543204B2
公开(公告)日：2009-06-02
申请号：US11191417
申请日：2005-07-28
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Steven Paul Jones , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Steven Paul Jones , Chad B. McBride
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318583
摘要： Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.
摘要翻译：提供了用于设计用于匹配时钟树的门控部分的逻辑扫描链的方法，装置和计算机程序产品。时钟树包括多个部分，每个部分包括接收用于特定扫描链的全局时钟和链专用时钟控制信号的输入的门。定义了多个扫描链，每个扫描链包括多个闩锁。每个扫描链锁存器连接到相应的链专用时钟树部分。

2. 发明申请

US20080141210A1 AUTOMATIC BACK ANNOTATION OF A FUNCTIONAL DEFINITION OF AN INTEGRATED CIRCUIT DESIGN BASED UPON PHYSICAL LAYOUT 审中-公开
标题翻译：基于物理布局的集成电路设计的功能定义的自动返回
公开(公告)号：US20080141210A1
公开(公告)日：2008-06-12
申请号：US12031999
申请日：2008-02-15
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus and program product automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译：基于从功能定义生成的物理布局，设备和程序产品自动返回注释电路设计的功能定义。电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。

3. 发明授权

US08196074B2 Heuristic clustering of circuit elements in a circuit design 有权
标题翻译：电路设计中电路元件的启发式聚类
公开(公告)号：US08196074B2
公开(公告)日：2012-06-05
申请号：US12406439
申请日：2009-03-18
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

4. 发明申请

US20090178014A1 HEURISTIC CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN 有权
标题翻译：电路设计中电路元件的整体聚焦
公开(公告)号：US20090178014A1
公开(公告)日：2009-07-09
申请号：US12406439
申请日：2009-03-18
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

5. 发明授权

US07398505B2 Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout 失效
标题翻译：基于物理布局的集成电路设计的功能定义的自动背面注释
公开(公告)号：US07398505B2
公开(公告)日：2008-07-08
申请号：US11348877
申请日：2006-02-07
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译：一种装置，程序产品和方法基于从功能定义生成的物理布局自动地回溯电路设计的功能定义。电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。

6. 发明授权

US07509611B2 Heuristic clustering of circuit elements in a circuit design 失效
标题翻译：电路设计中电路元件的启发式聚类
公开(公告)号：US07509611B2
公开(公告)日：2009-03-24
申请号：US11348970
申请日：2006-02-07
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

7. 发明授权

US07317683B2 Weighted fair queue serving plural output ports 失效
标题翻译：加权公平队列服务多个输出端口
公开(公告)号：US07317683B2
公开(公告)日：2008-01-08
申请号：US10015994
申请日：2001-11-01
申请人： William John Goetzinger , Glen Howard Handlogten , James Francis Mikos , David Alan Norgaard
发明人： William John Goetzinger , Glen Howard Handlogten , James Francis Mikos , David Alan Norgaard
IPC分类号： H04J1/16
CPC分类号： H04L49/30 , H04L47/2441 , H04L47/50 , H04L47/621 , H04L49/254
摘要： A data communication apparatus includes a plurality of output ports and a scheduler for assigning priorities for outbound data frames. The scheduler includes one or more scheduling queues. Each scheduling queue indicates an order in which data flows are to be serviced. At least one scheduling queue has a respective plurality of output ports assigned to the scheduling queue. That is, the scheduling queue is shared by two or more output ports.
摘要翻译：数据通信装置包括多个输出端口和用于分配出站数据帧的优先级的调度器。调度器包括一个或多个调度队列。每个调度队列指示数据流被维护的顺序。至少一个调度队列具有分配给调度队列的相应的多个输出端口。也就是说，调度队列由两个或更多个输出端口共享。

8. 发明授权

US07280474B2 Weighted fair queue having adjustable scaling factor 失效
标题翻译：加权公平队列具有可调缩放因子
公开(公告)号：US07280474B2
公开(公告)日：2007-10-09
申请号：US10015760
申请日：2001-11-01
申请人： William John Goetzinger , Glen Howard Handlogten , James Francis Mikos , David Alan Norgaard
发明人： William John Goetzinger , Glen Howard Handlogten , James Francis Mikos , David Alan Norgaard
IPC分类号： H04L12/26 , H04L12/56
CPC分类号： H04L47/2441 , H04L47/36 , H04L47/50 , H04L47/623
摘要： A scheduler for a network processor includes a scheduling queue in which weighted fair queuing is applied. The scheduling queue has a range R. Flows are attached to the scheduling queue at a distance D from a current pointer for the scheduling queue. The distance D is calculated for each flow according to the formula D=((WF×FS)/SF), where WF is a weighting factor applicable to a respective flow; FS is a frame size attributable to the respective flow; and SF is a scaling factor. The scaling factor SF is adjusted depending on a comparison of the distance D to the range R.
摘要翻译：网络处理器的调度器包括其中应用加权公平队列的调度队列。调度队列具有范围R.流量与调度队列的当前指针距离D附加到调度队列。根据公式D =（（WFxFS）/ SF）为每个流量计算距离D，其中WF是适用于相应流量的加权因子; FS是归因于相应流量的帧大小; SF是缩放因子。根据距离D与范围R的比较来调整缩放因子SF。

9. 发明授权

US5943249A Method and apparatus to perform pipelined denormalization of floating-point results 失效
标题翻译：执行浮点结果的流水线非规范化的方法和装置
公开(公告)号：US5943249A
公开(公告)日：1999-08-24
申请号：US843081
申请日：1997-04-25
申请人： Glen Howard Handlogten
发明人： Glen Howard Handlogten
IPC分类号： G06F5/01 , G06F7/52
CPC分类号： G06F5/012
摘要： A method of processing a floating-point instruction (including a multiply-add instruction) in a floating-point processor. Prior-art techniques require prenormalization of intermediate results generated by the floating-point processor, but normalization can sometimes result in an underflow condition, which requires denormalizing the intermediate result. The present invention provides a method of determining an amount to shift the mantissa of the intermediate result to obtain a final result while avoiding ever producing an exponent that is out of range. The invention also allows denormalized numbers to be stored in the floating-point registers in a denormalized form. The method of determining the shift amount first requires a determination of whether both, or only one, of the product and adder operands are denormalized. If both are denormalized, then the shift amount is equal to the addend alignment amount. If, however, at least one of these values is normalized, then a leading zero overlay is used to derive the shift amount.
摘要翻译：一种在浮点处理器中处理浮点指令（包括加法指令）的方法。现有技术需要由浮点处理器产生的中间结果进行正规化，但归一化有时会导致下溢条件，这需要对中间结果进行非规范化。本发明提供了一种确定用于移动中间结果的尾数以获得最终结果的量的方法，同时避免产生超出范围的指数。本发明还允许非正规化数字以非规格化的形式存储在浮点寄存器中。首先确定移位量的方法需要确定乘积和加法器操作数是否被非规范化。如果两者都非正规化，则移位量等于加数对准量。然而，如果这些值中的至少一个被归一化，则使用前导零覆盖来导出移位量。

10. 发明授权

US07362706B2 Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidth 有权
标题翻译：具有未充分利用带宽的虚拟路径的层次调度的方法和装置
公开(公告)号：US07362706B2
公开(公告)日：2008-04-22
申请号：US10317413
申请日：2002-12-12
申请人： Lyle Edwin Grosbach , Glen Howard Handlogten , James Francis Mikos , David Alan Norgaard
发明人： Lyle Edwin Grosbach , Glen Howard Handlogten , James Francis Mikos , David Alan Norgaard
IPC分类号： H04L12/26
CPC分类号： H04L47/50 , H04L2012/5679
摘要： A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.
摘要翻译：提供了一种方法和装置，用于实现对于ATM（小区）和IP（帧）调度工作的未充分利用的带宽的超额预订的虚拟路径的分级调度。调度器包括用于管道和自主流的第一日历和用于管道流的第二日历。从第一个日历识别管道或自主流的获胜者。对于确定的胜利者管道，检查管道队列以获得胜利管道的相关管道流量。响应于为胜利者管道识别空管道队列，将管道赢取信用额度分配给管道，而不将胜利者管道重新连接到第一个日历。然后从第一个日历识别下一个赢家。当从第二个日历识别获胜者管道流量，并且将管道信贷分配给胜利者管道的管道时，优胜者管道流程将被无延误地维护。

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