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1. 发明授权

US07543204B2 Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree 失效
标题翻译：用于设计用于匹配时钟树门控部分的逻辑扫描链的方法，装置和计算机程序产品
公开(公告)号：US07543204B2
公开(公告)日：2009-06-02
申请号：US11191417
申请日：2005-07-28
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Steven Paul Jones , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Steven Paul Jones , Chad B. McBride
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318583
摘要： Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.
摘要翻译：提供了用于设计用于匹配时钟树的门控部分的逻辑扫描链的方法，装置和计算机程序产品。时钟树包括多个部分，每个部分包括接收用于特定扫描链的全局时钟和链专用时钟控制信号的输入的门。定义了多个扫描链，每个扫描链包括多个闩锁。每个扫描链锁存器连接到相应的链专用时钟树部分。

2. 发明授权

US08196074B2 Heuristic clustering of circuit elements in a circuit design 有权
标题翻译：电路设计中电路元件的启发式聚类
公开(公告)号：US08196074B2
公开(公告)日：2012-06-05
申请号：US12406439
申请日：2009-03-18
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

3. 发明申请

US20090178014A1 HEURISTIC CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN 有权
标题翻译：电路设计中电路元件的整体聚焦
公开(公告)号：US20090178014A1
公开(公告)日：2009-07-09
申请号：US12406439
申请日：2009-03-18
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

4. 发明授权

US07398505B2 Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout 失效
标题翻译：基于物理布局的集成电路设计的功能定义的自动背面注释
公开(公告)号：US07398505B2
公开(公告)日：2008-07-08
申请号：US11348877
申请日：2006-02-07
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译：一种装置，程序产品和方法基于从功能定义生成的物理布局自动地回溯电路设计的功能定义。电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。

5. 发明授权

US07509611B2 Heuristic clustering of circuit elements in a circuit design 失效
标题翻译：电路设计中电路元件的启发式聚类
公开(公告)号：US07509611B2
公开(公告)日：2009-03-24
申请号：US11348970
申请日：2006-02-07
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.
摘要翻译：一种装置，程序产品和方法利用启发式聚类来生成电路元件对簇或组的分配，以优化所需的空间位置度量。例如，可以使用启发式聚类将电路元件（例如启用扫描的锁存器）分配给单独的扫描链，以优化用于电路设计的扫描架构中的扫描链的布局。

6. 发明申请

US20080141210A1 AUTOMATIC BACK ANNOTATION OF A FUNCTIONAL DEFINITION OF AN INTEGRATED CIRCUIT DESIGN BASED UPON PHYSICAL LAYOUT 审中-公开
标题翻译：基于物理布局的集成电路设计的功能定义的自动返回
公开(公告)号：US20080141210A1
公开(公告)日：2008-06-12
申请号：US12031999
申请日：2008-02-15
申请人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
发明人： Mark S. Fredrickson , Glen Howard Handlogten , Chad B. McBride
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An apparatus and program product automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.
摘要翻译：基于从功能定义生成的物理布局，设备和程序产品自动返回注释电路设计的功能定义。电路设计可以反向注释，例如通过在电路设计中的多个电路元件之间生成多个赋值，以及使用从电路设计生成的电路设计的物理定义为电路设计定义的多个信号功能定义，以及修改电路设计的功能定义，以将多个分配结合到功能定义中。

7. 发明授权

US09146835B2 Methods and systems with delayed execution of multiple processors 有权
标题翻译：延迟执行多个处理器的方法和系统
公开(公告)号：US09146835B2
公开(公告)日：2015-09-29
申请号：US13343809
申请日：2012-01-05
申请人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
发明人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
IPC分类号： G06F11/36 , G06F11/16
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译：第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。

8. 发明申请

US20130179720A1 MULTIPLE PROCESSOR DELAYED EXECUTION 有权
标题翻译：多处理器延迟执行
公开(公告)号：US20130179720A1
公开(公告)日：2013-07-11
申请号：US13343809
申请日：2012-01-05
申请人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
发明人： Mark D. Bellows , Mark S. Fredrickson , Scott D. Frei , Steven P. Jones , Chad B. McBride
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F5/065 , G06F11/1695 , G06F11/366 , G06F2205/067
摘要： A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.
摘要翻译：第一先入先出（FIFO）存储器可以从包括第一处理器的第一处理器组接收第一处理器输入。第一处理器组被配置为基于包括一组输入信号，时钟信号和相应数据的第一处理器输入来执行程序代码。第一FIFO可以存储第一处理器输入，并且可以根据第一延迟将第一处理器输入输出到第二FIFO存储器和第二处理器。第二FIFO存储器可以存储第一处理器输入，并且可以根据第二延迟将第一处理器输入输出到第三处理器。第二处理器可以执行程序代码的至少第一部分，并且第三处理器可以响应于第一处理器输入来执行程序代码的至少第二部分。

9. 发明申请

US20080307281A1 TRADING PROPENSITY-BASED CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN 审中-公开
标题翻译：电路设计中电路元件的交易基于特征的聚类
公开(公告)号：US20080307281A1
公开(公告)日：2008-12-11
申请号：US12191654
申请日：2008-08-14
申请人： Mark S. Fredrickson , Chad B. McBride
发明人： Mark S. Fredrickson , Chad B. McBride
IPC分类号： G01R31/28
CPC分类号： G01R31/318357 , G01R31/318536 , G06F17/5045
摘要： An apparatus and program product utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.
摘要翻译：装置和程序产品利用基于交易倾向的聚类算法来生成电路元件到集群或组的分配，以优化多个集群的空间分布。例如，可以使用基于交易倾向的聚类来将电路元件（诸如具有扫描功能的锁存器）分配给单独的扫描链，以优化用于集成电路设计的扫描架构中的扫描链的布局。

10. 发明授权

US07430699B2 Trading propensity-based clustering of circuit elements in a circuit design 有权
标题翻译：电路设计中电路元件的交易倾向聚类
公开(公告)号：US07430699B2
公开(公告)日：2008-09-30
申请号：US11348907
申请日：2006-02-07
申请人： Mark S. Fredrickson , Chad B. McBride
发明人： Mark S. Fredrickson , Chad B. McBride
IPC分类号： G01R31/28
CPC分类号： G01R31/318357 , G01R31/318536 , G06F17/5045
摘要： An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.
摘要翻译：装置，程序产品和方法利用基于交易倾向的聚类算法来生成电路元件到集群或组的分配，以优化多个集群的空间分布。例如，可以使用基于交易倾向的聚类来将电路元件（诸如具有扫描功能的锁存器）分配给单独的扫描链，以优化用于集成电路设计的扫描架构中的扫描链的布局。

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