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1. 发明授权

US06855608B1 Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效
标题翻译：制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法
公开(公告)号：US06855608B1
公开(公告)日：2005-02-15
申请号：US10463643
申请日：2003-06-17
申请人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
发明人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.
摘要翻译：制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。与衬底相邻的层可以是氧化物。在电荷捕获电介质上沉积多晶硅层。在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。植入位线，并在暴露的侧壁上制造绝缘间隔物。去除氧化物以在位线区域中的绝缘间隔物之间露出衬底，并且在其上制造导体以增强每个位线的导电性。

2. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

3. 发明授权

US06927145B1 Bitline hard mask spacer flow for memory cell scaling 有权
标题翻译：位线硬掩模间隔流程用于存储单元缩放
公开(公告)号：US06927145B1
公开(公告)日：2005-08-09
申请号：US10770673
申请日：2004-02-02
申请人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
发明人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
IPC分类号： H01L21/027 , H01L21/761 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和形成半导体器件的方法。半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

4. 发明授权

US07163860B1 Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device 有权
标题翻译：在电荷捕获电介质闪速存储器件中形成具有降低的氢含量的栅堆叠间隔物和电荷储存材料的方法
公开(公告)号：US07163860B1
公开(公告)日：2007-01-16
申请号：US10430471
申请日：2003-05-06
申请人： Tazrien Kamal , Yun Wu , Mark Ramsbey , Jean Yee-Mei Yang , Arvind Halliyal , Rinji Sugino , Hidehiko Shiraiwa , Fred T K Cheung
发明人： Tazrien Kamal , Yun Wu , Mark Ramsbey , Jean Yee-Mei Yang , Arvind Halliyal , Rinji Sugino , Hidehiko Shiraiwa , Fred T K Cheung
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L29/7923 , Y10S438/954
摘要： The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.
摘要翻译：本发明在一个实施例中涉及一种用于制造电荷俘获电介质闪存器件的方法，该器件包括提供半导体衬底，该半导体衬底上形成有包括电荷俘获介电电荷存储层和覆盖电荷的控制栅电极俘获介电电荷存储层; 至少在所述栅叠层上形成氧化层; 以及在所述栅极堆叠上沉积间隔层，其中所述沉积步骤沉积相对于常规间隔物材料的氢含量具有降低的氢含量的间隔物材料。

5. 发明授权

US07018896B2 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing 有权
标题翻译：紫外线阻挡层，用于在BEOL处理中减少SONOS双位闪存器件的紫外线充电
公开(公告)号：US07018896B2
公开(公告)日：2006-03-28
申请号：US10818112
申请日：2004-04-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L21/00
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括接触帽层或基本上不透紫外线的接触覆盖层的基本不透紫外不透明的子层。

6. 发明授权

US06774432B1 UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL 有权
标题翻译：紫外线阻挡层，用于降低BEOL中SONOS双位闪存器件的UV感应充电
公开(公告)号：US06774432B1
公开(公告)日：2004-08-10
申请号：US10358589
申请日：2003-02-05
申请人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
发明人： Minh V. Ngo , Tazrien Kamal , Mark T. Ramsbey , Arvind Halliyal , Jaeyong Park , Ning Cheng , Jeff P. Erhardt , Clarence B. Ferguson , Jeffrey A. Shields , Angela T. Hui , Robert A. Huertas , Tyagamohan Gottipati
IPC分类号： H01L29792
CPC分类号： H01L29/66833 , H01L21/28282 , H01L23/552 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.
摘要翻译：一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 SONOS闪存设备，包括SONOS闪存单元; 以及至少一个UV保护层，其中UV保护层包括基本上不透紫外线的材料。在一个实施例中，该装置包括基本上不透紫外线的接触盖层。

7. 发明授权

US07033957B1 ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices 有权
标题翻译： ONO制造工艺，用于增加闪存器件底部氧化物 - 衬底界面的氧含量
公开(公告)号：US07033957B1
公开(公告)日：2006-04-25
申请号：US10358586
申请日：2003-02-05
申请人： Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Inkuk Kang , Jaeyong Park , Rinji Sugino , Jean Y. Yang , Fred T K Cheung , Arvind Halliyal , Amir H. Jafarpour
发明人： Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Inkuk Kang , Jaeyong Park , Rinji Sugino , Jean Y. Yang , Fred T K Cheung , Arvind Halliyal , Amir H. Jafarpour
IPC分类号： H01L21/31
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/3144 , H01L29/513 , H01L29/792 , Y10S438/954
摘要： Process for reducing charge leakage in a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on the semiconductor substrate to form an oxide/silicon interface having a first oxygen content adjacent the oxide/silicon interface; treating the bottom oxide layer to increase the first oxygen content to a second oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer. In another embodiment, process for reducing charge leakage in a SONOS flash memory device, including forming a bottom oxide layer of an ONO structure on a surface of the semiconductor substrate having an oxide/silicon interface with a super-stoichiometric oxygen content adjacent the oxide/silicon interface; and depositing a nitride charge-storage layer on the bottom oxide layer.
摘要翻译：包括在一个实施例中，在半导体衬底上形成ONO结构的底部氧化物层以形成具有与氧化物/硅界面相邻的第一氧含量的氧化物/硅界面的方法，用于减少SONOS闪速存储器件中的电荷泄漏的方法; 处理底部氧化物层以将第一氧含量增加到邻近氧化物/硅界面的第二氧含量; 以及在底部氧化物层上沉积氮化物电荷存储层。在另一个实施方案中，用于减少SONOS闪速存储器件中的电荷泄漏的方法，包括在半导体衬底的表面上形成具有超化学计量氧含量的氧化物/硅界面的氧化物/硅界面的氧化物/ 硅界面; 以及在底部氧化物层上沉积氮化物电荷存储层。

8. 发明授权

US06958511B1 Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen 有权
标题翻译：闪速存储器件及其制造方法，其包括具有不同氮浓度的两个区域的底部氧化物层
公开(公告)号：US06958511B1
公开(公告)日：2005-10-25
申请号：US10679774
申请日：2003-10-06
申请人： Arvind Halliyal , Amir H. Jafarpour , Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Jaeyong Park
发明人： Arvind Halliyal , Amir H. Jafarpour , Hidehiko Shiraiwa , Tazrien Kamal , Mark Ramsbey , Jaeyong Park
IPC分类号： H01L21/28 , H01L21/31 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： Process of fabricating multi-bit charge trapping dielectric flash memory device, including forming on a semiconductor substrate a bottom oxide layer to define a substrate/oxide interface, in which the bottom oxide layer includes a first oxygen concentration and a first nitrogen concentration; and adding a quantity of nitrogen to the bottom oxide layer, whereby the bottom oxide layer includes a first region adjacent the charge storage layer and a second region adjacent the substrate/oxide interface, the second region having a second oxygen concentration and a second nitrogen concentration, in which the second nitrogen concentration exceeds the first nitrogen concentration, provided that the second nitrogen concentration does not exceed the second oxygen concentration. In one embodiment, the first nitrogen concentration is substantially zero.
摘要翻译：制造多位电荷俘获电介质闪存器件的方法，包括在半导体衬底上形成底部氧化物层以限定衬底/氧化物界面，其中底部氧化物层包括第一氧浓度和第一氮浓度; 并且向底部氧化物层添加一定量的氮，由此底部氧化物层包括与电荷存储层相邻的第一区域和与衬底/氧化物界面相邻的第二区域，第二区域具有第二氧浓度和第二氮浓度其中第二氮浓度超过第一氮浓度，条件是第二氮浓度不超过第二氧浓度。在一个实施方案中，第一氮浓度基本为零。

9. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

10. 发明授权

US06436768B1 Source drain implant during ONO formation for improved isolation of SONOS devices 有权
标题翻译：在ONO形成期间的源极漏极注入，以改善SONOS器件的隔离
公开(公告)号：US06436768B1
公开(公告)日：2002-08-20
申请号：US09893279
申请日：2001-06-27
申请人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
发明人： Jean Yee-Mei Yang , Mark T. Ramsbey , Emmanuil Manos Lingunis , Yider Wu , Tazrien Kamal , Yi He , Edward Hsia , Hidehiko Shiraiwa
IPC分类号： H01L21336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L27/11568 , H01L29/66833
摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.
摘要翻译：本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或在电荷俘获电介质的第三层上形成附加材料。

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