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1. 发明授权

US06552776B1 Photolithographic system including light filter that compensates for lens error 有权
标题翻译：光刻系统包括补偿透镜误差的滤光片
公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译：公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化数据以提供所需的光强度变化。本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

2. 发明授权

US06194768B1 High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure 失效
标题翻译：高介电常数栅极电介质，其上覆盖的钽栅极导体形成在牺牲结构的侧壁表面上
公开(公告)号：US06194768B1
公开(公告)日：2001-02-27
申请号：US09177867
申请日：1998-10-23
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L31119
CPC分类号： H01L29/518 , H01L21/28114 , H01L21/2815 , H01L21/823418 , H01L21/823437 , H01L29/495 , H01L29/66659
摘要： A transistor is provided having a gate conductor produced with ultra fine geometries. The gate conductor is metallic and is sized using deposition rather than photolithography. The deposition process can be closely controlled to achieve gate lengths less than a few tenths of a micron. The metallic gate conductor serves to source metal atoms during anneal of lightly doped drain regions. The metal atoms migrate to the gate dielectric directly beneath the gate conductor to convert the gate dielectric to a high K dielectric. The high K dielectric is substantially resistant to breakdown yet enjoys the benefits of high speed operation and low threshold turn-on.
摘要翻译：提供具有以超细几何形状制造的栅极导体的晶体管。栅极导体是金属的，其尺寸使用沉积而不是光刻。可以严格控制沉积过程以实现小于十分之几微米的栅极长度。金属栅极导体用于在轻掺杂漏极区退火期间引发金属原子。金属原子迁移到栅极导体正下方的栅极电介质，将栅极电介质转换成高K电介质。高K电介质基本上不会破坏，而且具有高速运行和低阈值开启的优点。

3. 发明授权

US6146983A Method of making semiconductor device having sacrificial salicidation layer 有权
标题翻译：制造具有牺牲性磺化层的半导体器件的方法
公开(公告)号：US6146983A
公开(公告)日：2000-11-14
申请号：US193619
申请日：1998-11-17
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L21/2652
摘要： The present invention is directed to a transistor having a stacked silicide metal and method of making same. In general, the method comprises forming a layer of nitrogen-bearing silicon dioxide above the gate conductor and the source and drain regions of a transistor. In one illustrative embodiment, the method further comprises forming a layer of titanium above at least the surface of the gate conductor and the source and drain regions. Thereafter, a layer of cobalt is formed above the layer of titanium. The transistor is then subjected to a heat treating process such that at least the layer of cobalt forms a metal silicide. Also disclosed herein is a partially formed transistor comprised of a gate conductor, a source region and a gate region. In one illustrative embodiment, the transistor is further comprised of a layer of nitrogen-bearing silicon dioxide formed above the gate conductor and the source and drain regions. The transistor further comprises a layer of titanium positioned adjacent the layer of nitrogen-bearing silicon dioxide and a layer of cobalt positioned adjacent the layer of titanium.
摘要翻译：本发明涉及具有叠层硅化物金属的晶体管及其制造方法。通常，该方法包括在栅极导体和晶体管的源极和漏极区域之上形成含氮二氧化硅层。在一个说明性实施例中，该方法还包括在至少栅极导体的表面和源极和漏极区域的上方形成钛层。此后，在钛层上形成一层钴。然后对晶体管进行热处理工艺，使得至少该钴层形成金属硅化物。本文还公开了由栅极导体，源极区和栅极区组成的部分形成的晶体管。在一个说明性实施例中，晶体管还包括形成在栅极导体和源极和漏极区之上的含氮二氧化硅层。晶体管还包括邻近含氮二氧化硅层定位的钛层和邻近钛层定位的钴层。

4. 发明授权

US6060345A Method of making NMOS and PMOS devices with reduced masking steps 失效
标题翻译：制造具有减少掩蔽步骤的NMOS和PMOS器件的方法
公开(公告)号：US6060345A
公开(公告)日：2000-05-09
申请号：US844924
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
摘要翻译：公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层，栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中。有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

5. 发明授权

US6051459A Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate 失效
标题翻译：使用N沟道栅极的选择性掺杂和激活来制造N沟道和P沟道IGFET的方法
公开(公告)号：US6051459A
公开(公告)日：2000-04-18
申请号：US803730
申请日：1997-02-21
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.
摘要翻译：公开了制造N沟道和P沟道IGFET的方法。该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层，在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。

6. 发明授权

US5962894A Trench transistor with metal spacers 失效
标题翻译：沟槽晶体管与金属间隔
公开(公告)号：US5962894A
公开(公告)日：1999-10-05
申请号：US30052
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L29/76 , H01L31/062
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

7. 发明授权

US5930634A Method of making an IGFET with a multilevel gate 失效
标题翻译：制造具有多级门的IGFET的方法
公开(公告)号：US5930634A
公开(公告)日：1999-07-27
申请号：US844927
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28052 , H01L29/42376 , H01L29/4925 , H01L29/6659 , H01L29/7833
摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
摘要翻译：公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极活跃区域。有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

8. 发明授权

US5877058A Method of forming an insulated-gate field-effect transistor with metal spacers 失效
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US5877058A
公开(公告)日：1999-03-02
申请号：US703272
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L29/6656
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

9. 发明授权

US5710054A Method of forming a shallow junction by diffusion from a silicon-based spacer 失效
标题翻译：通过从硅基间隔物扩散形成浅结的方法
公开(公告)号：US5710054A
公开(公告)日：1998-01-20
申请号：US703273
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L29/08 , H01L29/78 , H01L21/265 , H01L21/385
CPC分类号： H01L29/66575 , H01L21/2256 , H01L21/2257 , H01L21/28105 , H01L21/28114 , H01L29/0847 , H01L29/41783 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.
摘要翻译：公开了一种在IGFET中形成浅结的方法。该方法包括在第一导电类型的半导体衬底上形成栅极绝缘体，在栅极绝缘体上形成栅电极，在栅电极的边缘上形成侧壁绝缘体，在衬底上形成硅基间隔物，使得侧壁绝缘体分离并电隔离间隔物和栅电极，并将第二导电类型的掺杂剂从间隔物扩散到衬底中。扩散掺杂剂在衬底中形成第二导电类型的浅区域，并且浅结与栅电极的边缘基本上横向对齐。

10. 发明授权

US06188114B1 Method of forming an insulated-gate field-effect transistor with metal spacers 有权
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US06188114B1
公开(公告)日：2001-02-13
申请号：US09204016
申请日：1998-12-01
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L31119
CPC分类号： H01L29/41783 , H01L29/41775 , H01L29/66575 , H01L29/6659
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

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