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1. 发明授权

US06194768B1 High dielectric constant gate dielectric with an overlying tantalum gate conductor formed on a sidewall surface of a sacrificial structure 失效
标题翻译：高介电常数栅极电介质，其上覆盖的钽栅极导体形成在牺牲结构的侧壁表面上
公开(公告)号：US06194768B1
公开(公告)日：2001-02-27
申请号：US09177867
申请日：1998-10-23
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L31119
CPC分类号： H01L29/518 , H01L21/28114 , H01L21/2815 , H01L21/823418 , H01L21/823437 , H01L29/495 , H01L29/66659
摘要： A transistor is provided having a gate conductor produced with ultra fine geometries. The gate conductor is metallic and is sized using deposition rather than photolithography. The deposition process can be closely controlled to achieve gate lengths less than a few tenths of a micron. The metallic gate conductor serves to source metal atoms during anneal of lightly doped drain regions. The metal atoms migrate to the gate dielectric directly beneath the gate conductor to convert the gate dielectric to a high K dielectric. The high K dielectric is substantially resistant to breakdown yet enjoys the benefits of high speed operation and low threshold turn-on.
摘要翻译：提供具有以超细几何形状制造的栅极导体的晶体管。栅极导体是金属的，其尺寸使用沉积而不是光刻。可以严格控制沉积过程以实现小于十分之几微米的栅极长度。金属栅极导体用于在轻掺杂漏极区退火期间引发金属原子。金属原子迁移到栅极导体正下方的栅极电介质，将栅极电介质转换成高K电介质。高K电介质基本上不会破坏，而且具有高速运行和低阈值开启的优点。

2. 发明授权

US6146983A Method of making semiconductor device having sacrificial salicidation layer 有权
标题翻译：制造具有牺牲性磺化层的半导体器件的方法
公开(公告)号：US6146983A
公开(公告)日：2000-11-14
申请号：US193619
申请日：1998-11-17
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/28052 , H01L21/28518 , H01L29/665 , H01L21/2652
摘要： The present invention is directed to a transistor having a stacked silicide metal and method of making same. In general, the method comprises forming a layer of nitrogen-bearing silicon dioxide above the gate conductor and the source and drain regions of a transistor. In one illustrative embodiment, the method further comprises forming a layer of titanium above at least the surface of the gate conductor and the source and drain regions. Thereafter, a layer of cobalt is formed above the layer of titanium. The transistor is then subjected to a heat treating process such that at least the layer of cobalt forms a metal silicide. Also disclosed herein is a partially formed transistor comprised of a gate conductor, a source region and a gate region. In one illustrative embodiment, the transistor is further comprised of a layer of nitrogen-bearing silicon dioxide formed above the gate conductor and the source and drain regions. The transistor further comprises a layer of titanium positioned adjacent the layer of nitrogen-bearing silicon dioxide and a layer of cobalt positioned adjacent the layer of titanium.
摘要翻译：本发明涉及具有叠层硅化物金属的晶体管及其制造方法。通常，该方法包括在栅极导体和晶体管的源极和漏极区域之上形成含氮二氧化硅层。在一个说明性实施例中，该方法还包括在至少栅极导体的表面和源极和漏极区域的上方形成钛层。此后，在钛层上形成一层钴。然后对晶体管进行热处理工艺，使得至少该钴层形成金属硅化物。本文还公开了由栅极导体，源极区和栅极区组成的部分形成的晶体管。在一个说明性实施例中，晶体管还包括形成在栅极导体和源极和漏极区之上的含氮二氧化硅层。晶体管还包括邻近含氮二氧化硅层定位的钛层和邻近钛层定位的钴层。

3. 发明授权

US6127234A Ultra shallow extension formation using disposable spacers 有权
标题翻译：使用一次性间隔物的超浅延伸形成
公开(公告)号：US6127234A
公开(公告)日：2000-10-03
申请号：US226881
申请日：1999-01-07
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/336
CPC分类号： H01L29/6659
摘要： The present invention is directed to a method of forming ultra shallow extensions in a transistor and a device incorporating same. The method comprises forming a gate dielectric and a gate conductor above a surface of a semiconducting substrate and forming a first plurality of sidewall spacers adjacent the gate dielectric and the gate conductor. The method continues with implanting the substrate with a dopant material to form a plurality of doped regions in the substrate, heating the substrate to drive the dopant material towards the gate dielectric, and removing the first plurality of sidewall spacers. The method further comprises forming a second plurality of sidewall spacers adjacent the gate dielectric and the gate conductor, and performing a second ion implantation process to complete the formation of source/drain regions in said substrate. The present invention is also directed to a structure comprising a gate dielectric positioned above a surface of a semiconducting substrate, and a gate conductor positioned above the gate dielectric. The structure further comprises a plurality of sidewall spacers positioned adjacent the gate dielectric and the gate conductor, the sidewall spacers having a certain thickness. The structure further comprises a plurality of doped regions formed in the substrate that are laterally spaced apart from the gate dielectric by an amount corresponding to the approximate thickness of the sidewall spacers.
摘要翻译：本发明涉及一种在晶体管中形成超浅延伸的方法和结合其的器件。该方法包括在半导体衬底的表面之上形成栅极电介质和栅极导体，并形成邻近栅极电介质和栅极导体的第一多个侧壁间隔物。该方法继续用掺杂剂材料注入衬底以在衬底中形成多个掺杂区域，加热衬底以驱动掺杂剂材料朝向栅极电介质，以及去除第一多个侧壁间隔物。该方法还包括形成与栅极电介质和栅极导体相邻的第二多个侧壁间隔物，以及执行第二离子注入工艺以完成所述衬底中的源极/漏极区的形成。本发明还涉及一种包括位于半导体衬底的表面上方的栅极电介质和位于栅极电介质上方的栅极导体的结构。所述结构还包括邻近所述栅极电介质和所述栅极导体定位的多个侧壁间隔物，所述侧壁间隔物具有一定厚度。该结构还包括形成在衬底中的多个掺杂区域，其与栅极电介质横向间隔开相当于侧壁间隔物的近似厚度的量。

4. 发明授权

US06403445B1 Enhanced trench isolation structure 失效
标题翻译：增强沟槽隔离结构
公开(公告)号：US06403445B1
公开(公告)日：2002-06-11
申请号：US09286729
申请日：1999-04-06
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21762
CPC分类号： H01L21/76888 , H01L21/76224 , H01L21/76834 , H01L21/76895 , H01L21/823878
摘要： An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.
摘要翻译：对于一个实施例，沟槽隔离形成的改进方法包括在平坦化沟槽之上施加多晶硅层，并且在刻蚀有源区之前将多晶硅转化为氧化物。这种转化的氧化物比通常用于填充沟槽（例如TEOS）的材料更致密，并且导致较少的沟槽隔离区的过蚀刻。因此，电介质隔离的质量得到改善，特别是较小的漏电流流过沟槽隔离区。此外，较少的漏电流从随后形成的局部互连层流出。

5. 发明授权

US06268637B1 Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication 有权
标题翻译：通过制造用于低K隔离高级CMOS制造的横向EPI桥来制造气隙隔离的方法
公开(公告)号：US06268637B1
公开(公告)日：2001-07-31
申请号：US09178080
申请日：1998-10-22
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L2900
CPC分类号： H01L21/823878 , H01L21/764
摘要： An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and the substrate define an air gap in the trench. The isolation structure exhibits a low capacitance in a narrow structure. Scaling is enhanced and the potential for parasitic leakage current due to non-planarity is reduced.
摘要翻译：提供隔离结构及其制造方法。在一个方面，该方法包括以下步骤：在衬底中形成沟槽并在沟槽中形成第一绝缘侧壁，并在沟槽中形成与第一绝缘侧壁间隔开的第二绝缘体。桥接层形成在第一和第二侧壁之间。桥接层，第一和第二侧壁以及衬底在沟槽中限定气隙。隔离结构在窄结构中表现出低电容。缩放增强，并且由于非平面性引起的寄生漏电流的可能性降低。

6. 发明授权

US6084280A Transistor having a metal silicide self-aligned to the gate 有权
标题翻译：具有与栅极自对准的金属硅化物的晶体管
公开(公告)号：US6084280A
公开(公告)日：2000-07-04
申请号：US173233
申请日：1998-10-15
申请人： Mark I. Gardner , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardner , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28518 , H01L29/66545
摘要： A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening. According to one embodiment, the fill structures are removed and an interlevel dielectric is formed upon the transistor. In an alternative embodiment, the fill structures include a dielectric material and are retained as interlevel dielectrics. In a further embodiment, the fill structures include a conductive material and are retained as contacts between the source and drain areas and subsequently formed interconnects. The current transistor may be formed such that the metal silicide is aligned with the gate dielectric and is located in close proximity to the channel region.
摘要翻译：可以根据以下过程形成具有靠近沟道区的源极/漏极金属硅化物的晶体管。在半导体衬底上形成掩模结构，并且将金属沉积自对准到掩模结构的侧壁表面。然后将金属退火以形成金属硅化物。在形成与掩模结构的侧壁表面自对准的轻掺杂漏极杂质区域之后，可以在侧壁表面附近形成间隔物，并且可以将源极和漏极杂质区域形成为自对准到间隔物的侧壁表面。然后在间隔物附近形成填充结构，并且去除掩模结构以在间隔物之间形成开口。在开口内的半导体衬底的暴露的上表面上形成栅极电介质，并且在开口内形成栅极导体。根据一个实施例，去除填充结构，并在晶体管上形成层间电介质。在替代实施例中，填充结构包括电介质材料并保留为层间电介质。在另一个实施例中，填充结构包括导电材料并且被保持为源极和漏极区域之间的接触以及随后形成的互连。电流晶体管可以形成为使得金属硅化物与栅极电介质对准并且位于紧邻沟道区域。

7. 发明授权

US06410967B1 Transistor having enhanced metal silicide and a self-aligned gate electrode 有权
标题翻译：晶体管具有增强的金属硅化物和自对准栅电极
公开(公告)号：US06410967B1
公开(公告)日：2002-06-25
申请号：US09173273
申请日：1998-10-15
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L2972
CPC分类号： H01L29/66583 , H01L21/26586 , H01L29/41775 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66606
摘要： A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor. The process also allows formation of a metal gate conductor self-aligned with lightly doped drain or source-drain impurity areas.
摘要翻译：描述晶体管和制造晶体管的方法。在半导体衬底上形成金属层，在金属层上形成掩模层。图案化掩模层以在其中形成开口，并且去除未被掩模层覆盖的金属层的部分。在半导体衬底的开口内形成栅介质层; 在一个实施例中，间隔物也形成在掩蔽层的相对的侧壁表面上。然后将导电材料沉积在电介质材料上以形成栅极导体。然后去除掩模材料，在半导体衬底中形成源极和漏极以及轻掺杂的漏极杂质区域，并且将金属层退火以形成靠近沟道区的硅化物。通过在形成栅极导体之前沉积金属层，本文所述的工艺允许形成与晶体管的沟道区相邻或紧邻的金属硅化物。该工艺还允许形成与轻掺杂漏极或源极 - 漏极杂质区域自对准的金属栅极导体。

8. 发明授权

US06261908B1 Buried local interconnect 失效
标题翻译：埋地方互联
公开(公告)号：US06261908B1
公开(公告)日：2001-07-17
申请号：US09123177
申请日：1998-07-27
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L23/535 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate and forming a first insulating layer in the trench. A conductor layer is formed on the first insulating layer. A portion of the conductor layer is removed to define a local interconnect layer and a second insulating layer is formed in the trench covering the local interconnect layer. The method provides for a local interconnect layer buried beneath a dielectric layer of an integrated circuit, such as a shallow trench isolation layer. Areas of a substrate above the silicon-silicon dioxide interface formerly reserved for local interconnect layers in conventional processing may now be used for additional conductor lines.
摘要翻译：提供了一种在衬底中制造掩埋局部互连的方法和包括其的集成电路。该方法包括在衬底中形成沟槽并在沟槽中形成第一绝缘层的步骤。导体层形成在第一绝缘层上。去除导体层的一部分以限定局部互连层，并且在覆盖局部互连层的沟槽中形成第二绝缘层。该方法提供了埋在诸如浅沟槽隔离层的集成电路的介电层下面的局部互连层。以前用于常规处理中的局部互连层的硅 - 二氧化硅界面上方的衬底区域现在可用于附加的导体线。

9. 发明授权

US6140674A Buried trench capacitor 失效
标题翻译：埋沟电容器
公开(公告)号：US6140674A
公开(公告)日：2000-10-31
申请号：US123117
申请日：1998-07-27
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/334 , H01L21/762 , H01L27/06 , H01L29/94 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66181 , H01L21/76224 , H01L27/0623 , H01L29/945
摘要： An integrated circuit and a method of making the same are provided. The circuit includes a substrate that has a trench formed therein defining and isolating first and second active area and an upper surface. The circuit includes a capacitor that has a first insulating layer formed in the trench, a conductor layer formed on the first insulating layer, and a second insulating layer formed on the first insulating layer that fills the trench. The conductor layer is positioned substantially at or below the upper surface. The circuit integrates trench isolation structure with a capacitor that may be used as a filter between power and ground. The method integrates capacitor formation with trench isolation formation.
摘要翻译：提供集成电路及其制造方法。电路包括具有形成在其中的沟槽的衬底，其限定并隔离第一和第二有源区域和上表面。该电路包括具有形成在沟槽中的第一绝缘层的电容器，形成在第一绝缘层上的导体层，以及形成在填充沟槽的第一绝缘层上的第二绝缘层。导体层基本上位于上表面或下表面。该电路将沟槽隔离结构与可用作电源和地之间的滤波器的电容器集成。该方法集成了具有沟槽隔离形成的电容器形成。

10. 发明授权

US6114229A Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication 有权
标题翻译：多晶硅栅极电极在MOS晶体管制造中的关键尺寸和驱动电流控制
公开(公告)号：US6114229A
公开(公告)日：2000-09-05
申请号：US196845
申请日：1998-11-20
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/28 , H01L21/20 , H01L21/3205 , H01L21/36 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28035
摘要： A method is provided for controlling the critical dimensions of a polysilicon gate electrode, and for improving transistor drive current control. The method involves subjecting the gate structure of a transistor to a thermal treatment process in the presence of hydrogen gas. The thermal treatment process is performed subsequent to gate etching and photoresist mask removal, and provides gate electrodes having a more homogeneous linewidth, thereby improving transistor performance.
摘要翻译：提供了一种用于控制多晶硅栅电极的临界尺寸并提高晶体管驱动电流控制的方法。该方法包括在氢气存在下对晶体管的栅极结构进行热处理工艺。在栅极蚀刻和光致抗蚀剂掩模去除之后进行热处理工艺，并且提供具有更均匀的线宽的栅电极，从而提高晶体管性能。

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