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1. 发明授权

US09009020B1 Automatic identification of interesting interleavings in a multithreaded program 有权
标题翻译：在多线程程序中自动识别有趣的交错
公开(公告)号：US09009020B1
公开(公告)日：2015-04-14
申请号：US13047716
申请日：2011-03-14
申请人： Mark H. Oskin , Peter J. Godman , Andrew M. Schwerin , Andrew J. Whitaker , Lucas M. Kreger-Stickles , Kaya Bekiroglu
发明人： Mark H. Oskin , Peter J. Godman , Andrew M. Schwerin , Andrew J. Whitaker , Lucas M. Kreger-Stickles , Kaya Bekiroglu
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F9/455 , G06F8/4434 , G06F9/45504 , G06F9/461 , G06F9/4806 , G06F9/4825 , G06F2009/45575 , G06F2009/45591 , G06F2209/46 , G06F2209/483
摘要： A facility that for a multithreaded program executing on a root machine causes the threads of the program to be executed in a relative scheduling that produces an interesting result. The facility suspends execution of the program. The facility then tests a plurality of relative thread schedulings on one or more virtual machines and observes the result. Based upon the observed result the facility selects one of the tested relative thread schedulings. The facility then resumes execution of the program using the selected relative thread scheduling.
摘要翻译：用于在根机器上执行的多线程程序的功能使程序的线程在相关调度中执行，从而产生有趣的结果。该设施暂停执行该程序。该设备然后在一个或多个虚拟机上测试多个相对线程调度，并观察结果。根据观察结果，设备选择一个测试的相对线程调度。然后，该设备使用所选择的相对线程调度来恢复程序的执行。

2. 发明授权

US09086969B2 Establishing a useful debugging state for multithreaded computer program 有权
标题翻译：为多线程计算机程序建立一个有用的调试状态
公开(公告)号：US09086969B2
公开(公告)日：2015-07-21
申请号：US12969461
申请日：2010-12-15
申请人： Kaya Bekiroglu , Andrew M. Schwerin , Peter J. Godman , Mark H. Oskin
发明人： Kaya Bekiroglu , Andrew M. Schwerin , Peter J. Godman , Mark H. Oskin
IPC分类号： G06F9/44 , G06F11/07 , G06F11/36
CPC分类号： G06F11/079 , G06F11/36 , G06F11/3632 , G06F11/3636
摘要： A facility for supporting the analysis of a multithreaded program is described. For each of a number of threads of the multithreaded program, the facility identifies a semantically meaningful point in the execution of the thread. The facility interrupts the execution of each thread at the point identified for the thread.
摘要翻译：描述了支持多线程程序分析的工具。对于多线程程序的多个线程中的每一个，该设施识别线程执行中的语义上有意义的点。该设施在针对线程识别的点处中断每个线程的执行。

3. 发明申请

US20110179399A1 ESTABLISHING A USEFUL DEBUGGING STATE FOR MULTITHREADED COMPUTER PROGRAM 有权
标题翻译：建立多用途计算机程序的有效调试状态
公开(公告)号：US20110179399A1
公开(公告)日：2011-07-21
申请号：US12969461
申请日：2010-12-15
申请人： Kaya Bekiroglu , Andrew M. Schwerin , Peter J. Godman , Mark H. Oskin
发明人： Kaya Bekiroglu , Andrew M. Schwerin , Peter J. Godman , Mark H. Oskin
IPC分类号： G06F9/44
CPC分类号： G06F11/079 , G06F11/36 , G06F11/3632 , G06F11/3636
摘要： A facility for supporting the analysis of a multithreaded program is described. For each of a number of threads of the multithreaded program, the facility identifies a semantically meaningful point in the execution of the thread. The facility interrupts the execution of each thread at the point identified for the thread.
摘要翻译：描述了支持多线程程序分析的工具。对于多线程程序的多个线程中的每一个，该设施识别线程执行中的语义上有意义的点。该设施在针对线程识别的点处中断每个线程的执行。

4. 发明授权

US08453120B2 Enhanced reliability using deterministic multiprocessing-based synchronized replication 失效
标题翻译：使用基于确定性多进程的同步复制增强可靠性
公开(公告)号：US08453120B2
公开(公告)日：2013-05-28
申请号：US12778058
申请日：2010-05-11
申请人： Luis Ceze , Peter J. Godman , Mark H. Oskin
发明人： Luis Ceze , Peter J. Godman , Mark H. Oskin
IPC分类号： G06F9/45
CPC分类号： G06F11/366 , G06F9/467 , G06F9/524 , G06F11/3624 , G06F11/3632
摘要： A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.
摘要翻译：描述用于执行多线程程序的硬件和/或软件设施。该设备使得多个机器中的每一个确定性地执行多线程程序，使得多个机器的多线程程序的确定性执行被替换。该设备通过多台机器之一来检测执行多线程程序的问题。作为响应，该设施通过多个机器中的至少一个来调整多线程程序的执行。

5. 发明申请

US20110283262A1 ENHANCED RELIABILITY USING DETERMINISTIC MULTIPROCESSING-BASED SYNCHRONIZED REPLICATION 失效
标题翻译：使用基于确定性多媒体同步复制的增强可靠性
公开(公告)号：US20110283262A1
公开(公告)日：2011-11-17
申请号：US12778058
申请日：2010-05-11
申请人： Luis Ceze , Peter J. Godman , Mark H. Oskin
发明人： Luis Ceze , Peter J. Godman , Mark H. Oskin
IPC分类号： G06F9/44 , G06F11/36
CPC分类号： G06F11/366 , G06F9/467 , G06F9/524 , G06F11/3624 , G06F11/3632
摘要： A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.
摘要翻译：描述用于执行多线程程序的硬件和/或软件设施。该设备使得多个机器中的每一个确定性地执行多线程程序，使得多个机器的多线程程序的确定性执行被替换。该设备通过多台机器之一来检测执行多线程程序的问题。作为响应，该设施通过多个机器中的至少一个来调整多线程程序的执行。

6. 发明授权

US08694997B2 Deterministic serialization in a transactional memory system based on thread creation order 失效
标题翻译：基于线程创建顺序的事务内存系统中的确定性序列化
公开(公告)号：US08694997B2
公开(公告)日：2014-04-08
申请号：US12334336
申请日：2008-12-12
申请人： Luis H. Ceze , Mark H. Oskin
发明人： Luis H. Ceze , Mark H. Oskin
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/52 , G06F9/463 , G06F9/466 , G06F9/522 , G06F9/544
摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The facility may operate together with a transactional memory system. When the facility operates together with a transactional memory system, each quantum is encapsulated in a transaction that, may be executed concurrently with other transactions, and is committed according to the specified deterministic order.
摘要翻译：提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。该设施可以与事务存储系统一起操作。当设施与事务存储系统一起运行时，每个量子被封装在可以与其他事务同时执行的事务中，并且根据指定的确定性顺序被提交。

7. 发明授权

US08612955B2 Wavescalar architecture having a wave order memory 失效
标题翻译：波浪式建筑具有波浪记忆
公开(公告)号：US08612955B2
公开(公告)日：2013-12-17
申请号：US12017480
申请日：2008-01-22
申请人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
发明人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
IPC分类号： G06F9/45
CPC分类号： G06F9/5033 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3851 , G06F9/4494 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/526 , G06F15/8023 , G06F2209/5017 , G06F2209/521
摘要： A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
摘要翻译：数据流指令集架构和执行模型，被称为WaveScalar，其设计用于可扩展的低复杂度/高性能处理器，同时通过称为波次序存储器的机制有效地提供传统的存储器语义。波形存储器使得以任何语言编写的“现实世界”程序都可以在WaveScalar架构上运行，也可以执行任何无序执行单元。因为它是软件控制的，所以可以禁用波形顺序的内存来获得更大的并行性。 Wavescalar还包括一个软件控制的标签管理系统。

8. 发明申请

US20090165006A1 DETERMINISTIC MULTIPROCESSING 失效
标题翻译：决定性多媒体
公开(公告)号：US20090165006A1
公开(公告)日：2009-06-25
申请号：US12334336
申请日：2008-12-12
申请人： Luis H. Ceze , Mark H. Oskin
发明人： Luis H. Ceze , Mark H. Oskin
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/463 , G06F9/466 , G06F9/522 , G06F9/544
摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The facility may operate together with a transactional memory system. When the facility operates together with a transactional memory system, each quantum is encapsulated in a transaction that, may be executed concurrently with other transactions, and is committed according to the specified deterministic order.
摘要翻译：提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。该设施可以与事务存储系统一起操作。当设施与事务存储系统一起运行时，每个量子被封装在可以与其他事务同时执行的事务中，并且根据指定的确定性顺序被提交。

9. 发明授权

US07657882B2 Wavescalar architecture having a wave order memory 失效
标题翻译：波浪式建筑具有波浪记忆
公开(公告)号：US07657882B2
公开(公告)日：2010-02-02
申请号：US11041396
申请日：2005-01-21
申请人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
发明人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
IPC分类号： G06F9/45
CPC分类号： G06F9/5033 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3851 , G06F9/4494 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/526 , G06F15/8023 , G06F2209/5017 , G06F2209/521
摘要： A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
摘要翻译：数据流指令集架构和执行模型，被称为WaveScalar，其设计用于可扩展的低复杂度/高性能处理器，同时通过称为波次序存储器的机制有效地提供传统的存储器语义。波形存储器使得以任何语言编写的“现实世界”程序都可以在WaveScalar架构上运行，也可以执行任何无序执行单元。因为它是软件控制的，所以可以禁用波形顺序的内存来获得更大的并行性。 Wavescalar还包括一个软件控制的标签管理系统。

10. 发明授权

US08739163B2 Critical path deterministic execution of multithreaded applications in a transactional memory system 有权
标题翻译：交易内存系统中多线程应用程序的关键路径确定性执行
公开(公告)号：US08739163B2
公开(公告)日：2014-05-27
申请号：US12402395
申请日：2009-03-11
申请人： Luis Ceze , Mark H. Oskin , Joseph Luke Devietti , Brandon Michael Lucia
发明人： Luis Ceze , Mark H. Oskin , Joseph Luke Devietti , Brandon Michael Lucia
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/52 , G06F9/30087 , G06F11/3632
摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The deterministic number of operations may be adapted to follow the critical path of the multithreaded application. Specified memory operations may be executed regardless of the deterministic order, such as those accessing provably local data. The facility may provide dynamic bug avoidance and sharing of identified bug information.
摘要翻译：提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。可以将确定性的操作数量调整为遵循多线程应用程序的关键路径。可以执行指定的存储器操作，而不管确定性顺序如访问可证明的本地数据的那些。该设施可能会提供动态的错误回避和共享已识别的错误信息。

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