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1. 发明授权

US08453120B2 Enhanced reliability using deterministic multiprocessing-based synchronized replication 失效
标题翻译：使用基于确定性多进程的同步复制增强可靠性
公开(公告)号：US08453120B2
公开(公告)日：2013-05-28
申请号：US12778058
申请日：2010-05-11
申请人： Luis Ceze , Peter J. Godman , Mark H. Oskin
发明人： Luis Ceze , Peter J. Godman , Mark H. Oskin
IPC分类号： G06F9/45
CPC分类号： G06F11/366 , G06F9/467 , G06F9/524 , G06F11/3624 , G06F11/3632
摘要： A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.
摘要翻译：描述用于执行多线程程序的硬件和/或软件设施。该设备使得多个机器中的每一个确定性地执行多线程程序，使得多个机器的多线程程序的确定性执行被替换。该设备通过多台机器之一来检测执行多线程程序的问题。作为响应，该设施通过多个机器中的至少一个来调整多线程程序的执行。

2. 发明申请

US20110283262A1 ENHANCED RELIABILITY USING DETERMINISTIC MULTIPROCESSING-BASED SYNCHRONIZED REPLICATION 失效
标题翻译：使用基于确定性多媒体同步复制的增强可靠性
公开(公告)号：US20110283262A1
公开(公告)日：2011-11-17
申请号：US12778058
申请日：2010-05-11
申请人： Luis Ceze , Peter J. Godman , Mark H. Oskin
发明人： Luis Ceze , Peter J. Godman , Mark H. Oskin
IPC分类号： G06F9/44 , G06F11/36
CPC分类号： G06F11/366 , G06F9/467 , G06F9/524 , G06F11/3624 , G06F11/3632
摘要： A hardware and/or software facility for executing a multithreaded program is described. The facility causes each of a plurality of machines to execute the multithreaded program deterministically, such that the deterministic execution of the multithreaded program is replaced across the plurality of machines. The facility detects a problem in the execution of the multithreaded Program by one of the plurality of machines. In response, the facility adjusts the execution of the multithreaded program by at least one of the machines of the plurality.
摘要翻译：描述用于执行多线程程序的硬件和/或软件设施。该设备使得多个机器中的每一个确定性地执行多线程程序，使得多个机器的多线程程序的确定性执行被替换。该设备通过多台机器之一来检测执行多线程程序的问题。作为响应，该设施通过多个机器中的至少一个来调整多线程程序的执行。

3. 发明授权

US08739163B2 Critical path deterministic execution of multithreaded applications in a transactional memory system 有权
标题翻译：交易内存系统中多线程应用程序的关键路径确定性执行
公开(公告)号：US08739163B2
公开(公告)日：2014-05-27
申请号：US12402395
申请日：2009-03-11
申请人： Luis Ceze , Mark H. Oskin , Joseph Luke Devietti , Brandon Michael Lucia
发明人： Luis Ceze , Mark H. Oskin , Joseph Luke Devietti , Brandon Michael Lucia
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/52 , G06F9/30087 , G06F11/3632
摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The deterministic number of operations may be adapted to follow the critical path of the multithreaded application. Specified memory operations may be executed regardless of the deterministic order, such as those accessing provably local data. The facility may provide dynamic bug avoidance and sharing of identified bug information.
摘要翻译：提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。可以将确定性的操作数量调整为遵循多线程应用程序的关键路径。可以执行指定的存储器操作，而不管确定性顺序如访问可证明的本地数据的那些。该设施可能会提供动态的错误回避和共享已识别的错误信息。

4. 发明申请

US20090235262A1 EFFICIENT DETERMINISTIC MULTIPROCESSING 有权
标题翻译：有效的决策多媒体
公开(公告)号：US20090235262A1
公开(公告)日：2009-09-17
申请号：US12402395
申请日：2009-03-11
申请人： Luis Ceze , Mark H. Oskin , Joseph Luke Devietti , Brandon Michael Lucia
发明人： Luis Ceze , Mark H. Oskin , Joseph Luke Devietti , Brandon Michael Lucia
IPC分类号： G06F9/46 , G06F9/44 , G06F12/00 , G06F17/00
CPC分类号： G06F9/52 , G06F9/30087 , G06F11/3632
摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The deterministic number of operations may be adapted to follow the critical path of the multithreaded application. Specified memory operations may be executed regardless of the deterministic order, such as those accessing provably local data. The facility may provide dynamic bug avoidance and sharing of identified bug information.
摘要翻译：提供了用于控制多线程应用程序的线程在多处理系统上执行的操作顺序的硬件和/或软件设施。该设施可以串行化或选择性地串行化多线程应用的执行，使得在给多线程应用程序的相同输入时，多处理系统确定性地交织操作，从而在每次执行多线程应用程序时产生相同的输出。该设施将多线程应用程序代码的执行划分为指定确定性操作数的两个或多个量子，并且该设施指定线程执行两个或更多个量子的确定性顺序。可以将确定性的操作数量调整为遵循多线程应用程序的关键路径。可以执行指定的存储器操作，而不管确定性顺序如访问可证明的本地数据的那些。该设施可能会提供动态的错误回避和共享已识别的错误信息。

5. 发明申请

US20130145216A1 SYSTEMS AND METHODS FOR HARDWARE-ASSISTED TYPE CHECKING 有权
标题翻译：硬件辅助类型检查的系统和方法
公开(公告)号：US20130145216A1
公开(公告)日：2013-06-06
申请号：US13594607
申请日：2012-08-24
申请人： Susan J. Eggers , Luis Ceze , Emily Fortuna , Owen Anderson
发明人： Susan J. Eggers , Luis Ceze , Emily Fortuna , Owen Anderson
IPC分类号： G06F11/36
CPC分类号： G06F11/3668 , G06F8/437 , G06F11/0712 , G06F11/0772
摘要： Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.
摘要翻译：提供了为动态类型检查提供硬件支持的设备和方法。在一些实施例中，处理器包括类型检查寄存器和支持一个或多个被检查的加载指令。在一些实施例中，正常加载指令由具有检查的加载指令的编译器替代。在一些实施例中，为了执行检查的负载，错误处理程序指令位置被存储在类型检查寄存器中，并且类型标签操作数与存储在加载的存储单元中的类型标签进行比较。如果比较成功，执行可以正常进行。如果比较失败，则可以将执行转移到错误处理程序指令。在一些实施例中，执行类型预测以确定检查的加载指令是否可能失败。

6. 发明授权

US08327084B2 Method and apparatus to trigger synchronization and validation actions upon memory access 失效
标题翻译：在存储器访问时触发同步和验证动作的方法和装置
公开(公告)号：US08327084B2
公开(公告)日：2012-12-04
申请号：US11847917
申请日：2007-08-30
申请人： Christoph von Praun , Luis Ceze
发明人： Christoph von Praun , Luis Ceze
IPC分类号： G06F12/14 , G06F12/10
CPC分类号： G06F12/084 , G06F12/0842 , G06F12/1027 , G06F12/109 , G06F12/1466
摘要： A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.
摘要翻译：在一方面，触发在存储器访问中的同步和验证动作的系统和方法，识别与由线程访问的共享存储器区域相关联的存储类，确定线程是否保存存储类并获取存储类，如果线程不保存存储类，识别与存储类和线程相关联的可编程动作，并触发可编程动作。一个或多个存储类别分别与共享存储器的一个或多个区域相关联。与线程相关联的一组存储类保存线程获取的一个或多个存储类。与线程相关联的可配置动作表指示与存储类相关联的一个或多个可编程动作。

7. 发明授权

US08745440B1 Computer-implemented system and method for providing software fault tolerance 失效
标题翻译：用于提供软件容错的计算机实现的系统和方法
公开(公告)号：US08745440B1
公开(公告)日：2014-06-03
申请号：US13239281
申请日：2011-09-21
申请人： Luis Ceze , Peter Godman , Mark Oskin
发明人： Luis Ceze , Peter Godman , Mark Oskin
IPC分类号： G06F11/00
CPC分类号： G06F9/3842 , G06F9/3851 , G06F11/1492 , G06F11/1658
摘要： A computer-implemented method for providing software fault tolerance is provided. A multithreaded program is executed. The program execution includes a plurality of multithreaded processes. A set of inputs is provided to one of the multithreaded processes and the inputs set is copied to each of the other multithreaded processes. The executions of the multithreaded processes are divided into deterministic subsets of the execution that end at a checkpoint. An execution of the deterministic subset is speculatively executed continuously on one of the multithreaded processes. Upon completion of execution through the checkpoint, the successfully completed execution path through the deterministic subset is retired. Execution of the deterministic instructions subset on the other multithreaded process is continued along the completed execution path.
摘要翻译：提供了一种用于提供软件容错的计算机实现方法。执行多线程程序。程序执行包括多个多线程处理。将一组输入提供给多线程进程之一，并将输入集复制到其他多线程进程的每一个。多线程进程的执行被划分为在检查点处结束的执行的确定性子集。在多线程过程之一上连续推测地执行确定性子集的执行。在通过检查点完成执行后，通过确定性子集的成功完成的执行路径已经退休。在完成的执行路径上继续执行其他多线程进程上的确定性指令子集。

8. 发明授权

US08832659B2 Systems and methods for finding concurrency errors 有权
标题翻译：查找并发错误的系统和方法
公开(公告)号：US08832659B2
公开(公告)日：2014-09-09
申请号：US13312844
申请日：2011-12-06
申请人： Luis Ceze , Brandon Lucia
发明人： Luis Ceze , Brandon Lucia
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/75 , G06F8/314 , G06F11/3688
摘要： Systems and methods for detecting concurrency bugs are provided. In some embodiments, context-aware communication graphs that represent inter-thread communication are collected during test runs, and may be labeled according to whether the test run was correct or failed. Graph edges that are likely to be associated with failed behavior are determined, and probable reconstructions of failed behavior are constructed to assist in debugging. In some embodiments, software instrumentation is used to collect the communication graphs. In some embodiments, hardware configured to collect the communication graphs is provided.
摘要翻译：提供了检测并发错误的系统和方法。在一些实施例中，表示线程间通信的上下文感知通信图在测试运行期间被收集，并且可以根据测试运行是正确还是失败来标记。确定可能与故障行为相关联的图形边缘，并构建故障行为的可能重建以辅助调试。在一些实施例中，使用软件仪器来收集通信图。在一些实施例中，提供了被配置为收集通信图形的硬件。

9. 发明申请

US20120304159A1 HARDWARE SUPPORT FOR HASHTABLES IN DYNAMIC LANGUAGES 有权
标题翻译：动态语言中硬件支持的硬件支持
公开(公告)号：US20120304159A1
公开(公告)日：2012-11-29
申请号：US13181712
申请日：2011-07-13
申请人： Luis Ceze , Mohammad H. Reshadi , Thomas Sartorius
发明人： Luis Ceze , Mohammad H. Reshadi , Thomas Sartorius
IPC分类号： G06F9/45
CPC分类号： G06F8/44 , G06F8/31 , G06F9/4492
摘要： The aspects enable a computing device to execute traditionally software-based JavaScript® operations in hardware. Each JavaScript® object is hashed into a master hashtable that may be stored in the software. A portion of the software hashtable may be pushed to a hardware hashtable using special instruction set registers dedicated to hashtable processing. Each time a software process requests a hashtable operation (e.g., lookup) the hardware hashtable is checked to determine if the value exists in hardware. If the requested value is in the hardware hashtable, the requested value is accessed in a single operation step. If the requested value is not in the hardware hashtable, the requested value is extracted from the master hashtable in the software and a portion of the master hashtable containing the extracted value is pushed to the hardware using special instruction set registers.
摘要翻译：这些方面使计算设备能够在硬件中执行传统的基于软件的JavaScript®操作。每个JavaScript®对象被散列成可以存储在软件中的主哈希表。可以使用专用于散列表处理的专用指令集寄存器将软件散列表的一部分推送到硬件散列表。每当软件进程请求哈希表操作（例如，查找）时，检查硬件散列表以确定该值是否存在于硬件中。如果请求的值在硬件哈希表中，则在单个操作步骤中访问所请求的值。如果请求的值不在硬件哈希表中，则从软件中的主哈希表中提取所请求的值，并且使用特殊指令集寄存器将包含提取的值的主要哈希表的一部分推送到硬件。

10. 发明申请

US20090063783A1 METHOD AND APPARTAUS TO TRIGGER SYNCHRONIZATION AND VALIDATION ACTIONS UPON MEMORY ACCESS 失效
标题翻译：在存储器访问之前触发同步和验证操作的方法和步骤
公开(公告)号：US20090063783A1
公开(公告)日：2009-03-05
申请号：US11847917
申请日：2007-08-30
申请人： Christoph von Praun , Luis Ceze
发明人： Christoph von Praun , Luis Ceze
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0842 , G06F12/1027 , G06F12/109 , G06F12/1466
摘要： A system and method to trigger synchronization and validation actions at memory access, in one aspect, identifies a storage class associated with a region of shared memory being accessed by a thread, determines whether the thread holds the storage class and acquires the storage class if the thread does not hold the storage class, identifies a programmable action associated with the storage class and the thread, and triggers the programmable action. One or more storage classes are respectively associated with one or more regions of shared memory. An array of storage classes associated with a thread holds one or more storage classes acquired by the thread. A configurable action table associated with a thread indicates one or more programmable actions associated with a storage class.
摘要翻译：在一方面，触发在存储器访问中的同步和验证动作的系统和方法，识别与由线程访问的共享存储器区域相关联的存储类，确定线程是否保存存储类并获取存储类，如果线程不保存存储类，识别与存储类和线程相关联的可编程动作，并触发可编程动作。一个或多个存储类别分别与共享存储器的一个或多个区域相关联。与线程相关联的一组存储类保存线程获取的一个或多个存储类。与线程相关联的可配置动作表指示与存储类相关联的一个或多个可编程动作。

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