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1. 发明授权

US10198333B2 Test, validation, and debug architecture 有权
公开(公告)号：US10198333B2
公开(公告)日：2019-02-05
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

2. 发明申请

US20150127983A1 TEST, VALIDATION, AND DEBUG ARCHITECTURE 审中-公开
标题翻译：测试，验证和调试架构
公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译：这里描述了一种用于提供测试，验证和调试架构的装置和方法。在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。此外，该架构可能提供对测试架构的分层（多级）安全访问。此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

3. 发明申请

US20150269109A1 METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRANSACTION LAYER PACKETS 有权
标题翻译：方法，交易层单层通信的装置和系统
公开(公告)号：US20150269109A1
公开(公告)日：2015-09-24
申请号：US14658026
申请日：2015-03-13
申请人： Bryan L. Spry , Su Wei Lim , Mikal C. Hunsaker , Rohit R. Verma , Lily P. Looi , Ronald W. Swartz , Michael W. Leddige , Vui Yong Liew
发明人： Bryan L. Spry , Su Wei Lim , Mikal C. Hunsaker , Rohit R. Verma , Lily P. Looi , Ronald W. Swartz , Michael W. Leddige , Vui Yong Liew
IPC分类号： G06F13/42 , G06F13/40
CPC分类号： G06F13/4221 , G06F13/122 , G06F13/4022 , G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.
摘要翻译：用于与集成电路封装的协议栈交换单端通信的技术和机制。在一个实施例中，集成电路（IC）芯片包括协议栈，其包括执行与外围组件互连Express（PCIe TM）规范兼容的操作的事务层。在事务层和协议栈的链路层之间交换的事务层数据包与PCIe™格式兼容。在另一个实施例中，协议栈的物理层是将IC芯片耦合到另一个IC芯片，用于通过单端通信交换事务层分组。封装的器件包括两个IC芯片。

4. 发明授权

US06230226B1 Compound device implementing hub and function endpoints on a single chip 失效
标题翻译：复合器件在单个芯片上实现集线器和功能端点
公开(公告)号：US06230226B1
公开(公告)日：2001-05-08
申请号：US08940540
申请日：1997-09-30
申请人： King Seng Hu , Vui Yong Liew , Bruce Moore , Thomas Ohe
发明人： King Seng Hu , Vui Yong Liew , Bruce Moore , Thomas Ohe
IPC分类号： G06F1300
CPC分类号： G06F13/4022
摘要： A system and apparatus combining a hub and a function as a single chip compound device. A single serial interface engine (SIE) is shared between a hub endpoint and a function endpoint. The hub endpoint and function endpoint being integrated on a single chip. A single backend interface is coupled between the SIE and the endpoints. The backend interface selects which of the hub endpoints or the function endpoints can access the shared SIE at any time period. In one embodiment, a first address is associated with the hub and a second address is associated with the function. The backend interface selects between the hub and function by comparing a translated address received from the SIE with each of the first address and the second address. The result of the comparisons via suitable combinational logic serves as a select signal for a multiplexer between the hub/function and the SIE.
摘要翻译：将集线器和功能组合为单芯片复合器件的系统和装置。单个串行接口引擎（SIE）在集线器端点和功能端点之间共享。集线器端点和功能端点集成在单个芯片上。单个后端接口连接在SIE和端点之间。后端接口选择哪个集线器端点或功能端点可以在任何时间段访问共享SIE。在一个实施例中，第一地址与集线器相关联，并且第二地址与该功能相关联。后端接口通过将从SIE接收的转换地址与第一地址和第二地址中的每一个进行比较，在集线器和功能之间进行选择。通过适当的组合逻辑进行比较的结果可作为集线器/功能与SIE之间的多路复用器的选择信号。

5. 发明申请

US20220018901A1 TECHNIQUES TO ENABLE INTEGRATED CIRCUIT DEBUG ACROSS LOW POWER STATES 有权
公开(公告)号：US20220018901A1
公开(公告)日：2022-01-20
申请号：US17377264
申请日：2021-07-15
申请人： Keith A. Jones , Wai Mun Ng , Thomas A. Lyda , Subinlal Pk , Sankaran Menon , Vui Yong Liew , Kristan K. Wiseley
发明人： Keith A. Jones , Wai Mun Ng , Thomas A. Lyda , Subinlal Pk , Sankaran Menon , Vui Yong Liew , Kristan K. Wiseley
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3183
摘要： An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

6. 发明申请

US20130083804A1 MANAGING SIDEBAND ROUTERS IN ON-DIE SYSTEM FABRIC 有权
公开(公告)号：US20130083804A1
公开(公告)日：2013-04-04
申请号：US13631871
申请日：2012-09-29
申请人： Kay Keat Khoo , Vui Yong Liew , Hai Ming Khor
发明人： Kay Keat Khoo , Vui Yong Liew , Hai Ming Khor
IPC分类号： H04L12/56
CPC分类号： H04L45/60 , G06F13/38 , H04L12/6418 , H04L49/109
摘要： Methods and apparatus for managing sideband routers in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF router is configurable during runtime based, at least in part, on information stored in a table accessible by an agent coupled to the sideband OSF router. Other embodiments are also disclosed.

7. 发明授权

US5652894A Method and apparatus for providing power saving modes to a pipelined processor 失效
标题翻译：用于向流水线处理器提供省电模式的方法和装置
公开(公告)号：US5652894A
公开(公告)日：1997-07-29
申请号：US536087
申请日：1995-09-29
申请人： King Seng Hu , Vui Yong Liew
发明人： King Seng Hu , Vui Yong Liew
IPC分类号： G06F11/14 , G06F1/32
CPC分类号： G06F9/4418 , Y02B60/186
摘要： A clock and reset unit for providing power saving modes to a pipelined microprocessor and for guaranteeing that power saving instruction is the last to be executed before the clocks stop, upon wake-up the next instruction executed is the first instruction in the interrupt service routine (ISR) and that upon return from the ISR, the instruction immediately following the power saving instruction is executed. A register is provided in the clock and reset unit for initiating a power saving mode. A software programmer selects a particular power saving mode by setting a corresponding bit in this register (i.e., writing a predetermined value to this register). A processor stalling signal generator for generating a signal that indicates to the processor that the peripheral is not ready to process a processor request (thereby causing the processor to insert wait states until the peripheral is ready) is provided. The clock and reset unit is also provided a signal from an interrupt handler indicating that the processor will be executing the ISR upon leaving the power save instruction. In response to this signal, the clock and reset unit de-assert the wait state request and brought the processor out of the power saving instruction.
摘要翻译：一种时钟和复位单元，用于向流水线微处理器提供省电模式，并且用于保证在停止时钟之前最后执行的省电指令，在唤醒时，执行的下一指令是中断服务程序中的第一条指令（ ISR），并且从ISR返回时，执行紧接在省电指令之后的指令。在时钟和复位单元中提供一个寄存器，用于启动省电模式。软件编程器通过在该寄存器中设置相应的位（即向该寄存器写入预定值）来选择特定的省电模式。一种处理器停止信号发生器，用于产生一个信号，该信号向处理器指示外围设备未准备好处理处理器请求（从而使处理器插入等待状态，直到外设准备就绪）。时钟和复位单元还提供来自中断处理器的信号，指示处理器在离开省电指令时将执行ISR。响应该信号，时钟和复位单元解除等待状态请求，并使处理器退出省电指令。

8. 发明授权

US07296101B2 Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device 有权
标题翻译：用于使用补丁模块来处理非发布请求周期并控制返回到请求设备的完成的方法和系统
公开(公告)号：US07296101B2
公开(公告)日：2007-11-13
申请号：US10781512
申请日：2004-02-17
申请人： Chee Siong Lee , Vui Yong Liew , Mikal C. Hunsaker , Michael N. Derr
发明人： Chee Siong Lee , Vui Yong Liew , Mikal C. Hunsaker , Michael N. Derr
IPC分类号： G06F5/00
CPC分类号： G06F12/0638
摘要： A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.
摘要翻译：描述了一种系统，用于在输入/输出（I / O）控制器内提供补丁机制，可用于解决I / O控制器中存在的缺陷和状况。该系统包括耦合到包括在I / O控制器中的完成队列的补丁模块。补丁模块用于对I / O控制器接收的进入周期进行采样，并确定捕获的进入周期是否匹配一个或多个预编程触发条件。补丁模块能够通过控制加载到完成队列中的头信息并通过指示完成队列来确定是否丢弃从指定的终端设备接收到的完成，来围绕捕获的非发布请求周期进行操作。

9. 发明授权

US6088811A Method and apparatus for generating both a uniform duty cycle clock and a variable duty cycle clock using a single state machine 失效
标题翻译：用于使用单一状态机产生均匀占空比时钟和可变占空比时钟的方法和装置
公开(公告)号：US6088811A
公开(公告)日：2000-07-11
申请号：US941796
申请日：1997-09-30
申请人： Vui Yong Liew , Venkat Iyer
发明人： Vui Yong Liew , Venkat Iyer
IPC分类号： G06F1/08 , H03K5/156 , H03L7/08 , G06F1/04
CPC分类号： H03L7/08 , G06F1/08 , H03K5/1565 , H03L2207/50
摘要： A method and apparatus for generating both a uniform duty cycle clock and a variable duty cycle clock with a single state machine. A single state machine is provided having a series of states through which it transitions when in a first mode. The series of states causes the output of the state machine to be a uniform duty cycle clock signal. The state machine has a second group of states through which it transitions in a second mode. A transition scheme among the second group of states permits the duty cycle of a state machine output clock signal to vary.
摘要翻译：一种用单一状态机产生均匀占空比时钟和可变占空比时钟的方法和装置。提供具有一系列状态的单一状态机，当处于第一模式时，该状态机通过该状态转换。一系列状态导致状态机的输出为均匀的占空比时钟信号。状态机具有第二组状态，通过它们在第二模式中转换。第二组状态之间的转换方案允许状态机输出时钟信号的占空比变化。

10. 发明授权

US5987617A Low ICC enumeration scheme for bus powered USB device 失效
标题翻译：总线供电USB设备的低ICC枚举方案
公开(公告)号：US5987617A
公开(公告)日：1999-11-16
申请号：US940538
申请日：1997-09-30
申请人： King-Seng Hu , Lay Leng Cheok , Vui Yong Liew , Joseph Murray , Bruce Moore , Joseph Gaubatz
发明人： King-Seng Hu , Lay Leng Cheok , Vui Yong Liew , Joseph Murray , Bruce Moore , Joseph Gaubatz
IPC分类号： G06F1/32
CPC分类号： G06F1/325 , G06F1/32 , G06F1/3253 , Y02B60/1235 , Y02B60/32
摘要： An apparatus and method of reducing power consumption in an integrated device having a first module with a mandatory operating frequency and a second module with a flexible frequency requirement. The integrated device is powered by a serial bus. The first module is segregated from the second module in the time domain by a frequency independent interface. The second module is then operated at a lower frequency when power conservation is needed. The operating frequency of the second module can be dynamically changed to improve performance of the second module when a power budget for the device permits.
摘要翻译：一种在具有强制性操作频率的第一模块和具有灵活频率要求的第二模块的集成装置中降低功耗的装置和方法。集成设备由串行总线供电。第一个模块通过独立于频率的接口在时域与第二个模块隔离。然后，当需要节电时，第二个模块以较低的频率工作。当设备的功率预算允许时，可以动态地改变第二模块的工作频率以提高第二模块的性能。

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