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1. 发明授权

US10198333B2 Test, validation, and debug architecture 有权
公开(公告)号：US10198333B2
公开(公告)日：2019-02-05
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Brian Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

2. 发明申请

US20150127983A1 TEST, VALIDATION, AND DEBUG ARCHITECTURE 审中-公开
标题翻译：测试，验证和调试架构
公开(公告)号：US20150127983A1
公开(公告)日：2015-05-07
申请号：US13997182
申请日：2010-12-23
申请人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
发明人： Mark B. Trobough , Keshavan K. Tiruvallur , Chinna B. Prudvi , Christian E. Iovin , David W. Grawrock , Jay J. Nejedlo , Ashok N. Kabadi , Travis K. Goff , Evan J. Halprin , Kapila B. Udawatta , Jiun Long Foo , Wee Hoo Cheah , Vui Yong Liew , Selvakumar Raja Gopal , Yuen Tat Lee , Samie B. Samaan , Kip C. Killpack , Neil Dobler , Nagib Z. Hakim , Briar Meyer , William H. Penner , John L. Baudrexl , Russell J. Wunderlich , James J. Grealish , Kyle Markley , Timothy S. Storey , Loren J. McConnell , Lyle E. Cool , Mukesh Kataria , Rahima K. Mohammed , Tieyu Zheng , Yi Amy Xia , Ridvan A. Sahan , Arun R. Ramadorai , Priyadarsan Patra , Edwin E. Parks , Abhijit Davare , Padmakumar Gopal , Bruce Querbach , Hermann W. Gartler , Keith Drescher , Sanjay S. Salem , David C. Florey
IPC分类号： G06F11/273
CPC分类号： G06F11/2733 , G06F11/267
摘要： An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.
摘要翻译：这里描述了一种用于提供测试，验证和调试架构的装置和方法。在目标或基础级别，硬件（测试设计或DFx）被设计并集成在硅部件中。控制器可以提供对这种钩子的抽象访问，例如通过抽象层来抽象硬件DFx的低级细节。此外，通过接口（如API）的抽象层向更高级的软件/表示层提供服务，例程和数据结构，这些层能够收集测试数据，以便对被测单元/平台进行验证和调试。此外，该架构可能提供对测试架构的分层（多级）安全访问。此外，可以通过使用统一的双向测试访问端口来简化对平台的测试架构的物理访问，同时还可能允许远程访问执行被测部件/平台的远程测试和脱离。本质上描述了一个完整的测试架构栈，用于电子部件，设备和平台的测试，验证和调试。

3. 发明授权

US07208936B2 Socket lid and test device 失效
标题翻译：插座盖和测试装置
公开(公告)号：US07208936B2
公开(公告)日：2007-04-24
申请号：US10823049
申请日：2004-04-12
申请人： Kurt R. Goldsmith , James J. Grealish
发明人： Kurt R. Goldsmith , James J. Grealish
IPC分类号： G01R31/02
CPC分类号： G01R31/045 , G01R1/0433 , G01R31/2808 , G01R35/00
摘要： Various embodiments related to an integrated lid and test device for a socket, such as a land grid array (LGA) socket, that functions as a lid, as a testing device, and/or as a pick and place lid. Specifically, the integrated lid may provide test capability, in manufacturing of the socket and/or a printed circuit board (PCB) such as a motherboard, onto which the socket is attached. Thus the integrated lid may allow for testing the socket and/or the PCB for correct assembly and connectivity without requiring removal of the integrated lid to insert a test device prior to testing, or removal of a test device and replacement of the lid after testing.
摘要翻译：涉及用作插座的集成盖和测试装置的各种实施例，例如用作盖的地面栅格阵列（LGA）插座，作为测试装置和/或拾取和放置盖。具体来说，一体化盖可以在插座和/或诸如母板的印刷电路板（PCB）的制造中提供测试能力，插座附接到该主板上。因此，集成的盖可以允许测试插座和/或PCB以进行正确的组装和连接，而不需要在测试之前去除集成的盖以插入测试装置，或者在测试之后移除测试装置和更换盖子。

4. 发明授权

US5794007A System and method for programming programmable electronic components using board-level automated test equipment 失效
标题翻译：使用电路板级自动化测试设备编程可编程电子元件的系统和方法
公开(公告)号：US5794007A
公开(公告)日：1998-08-11
申请号：US553017
申请日：1995-11-03
申请人： George L. Arrigotti , James J. Grealish
发明人： George L. Arrigotti , James J. Grealish
IPC分类号： G01R31/3193 , G06F9/445 , G06F13/00
CPC分类号： G06F9/4401 , G01R31/3193
摘要： A system and technique utilized to efficiently load data into a programmable electronic component connected to a circuit board through the use of automated test equipment. The system includes an automated testing equipment and a programmable electronic component coupled to data and address lines utilized by the programmable electronic component. For the first circuit board of a batch of multiple circuit boards, the reference programmable electronic component receives and stores data from an external source, prior to the data being loaded from the reference programmable electronic component into the programmable electronic component. Thereafter, further programming of the reference programmable electronic component is not required. Rather, the programmable electronic component coupled to any subsequent circuit boards requires only the reference programmable electronic component to copy its contents upon receiving address and control signals from the external source to perform such an operation.
摘要翻译：用于通过使用自动测试设备将数据有效地加载到连接到电路板的可编程电子部件中的系统和技术。该系统包括自动测试设备和耦合到由可编程电子组件使用的数据和地址线的可编程电子组件。对于一批多个电路板的第一个电路板，参考可编程电子部件在将数据从参考可编程电子部件加载到可编程电子部件之前接收并存储来自外部源的数据。此后，不需要进一步编程参考可编程电子部件。相反，耦合到任何后续电路板的可编程电子部件仅在参考可编程电子部件从外部源接收地址和控制信号时才复制其内容，以执行这样的操作。

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