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1. 发明授权

US07296101B2 Method and system for using a patch module to process non-posted request cycles and to control completions returned to requesting device 有权
标题翻译：用于使用补丁模块来处理非发布请求周期并控制返回到请求设备的完成的方法和系统
公开(公告)号：US07296101B2
公开(公告)日：2007-11-13
申请号：US10781512
申请日：2004-02-17
申请人： Chee Siong Lee , Vui Yong Liew , Mikal C. Hunsaker , Michael N. Derr
发明人： Chee Siong Lee , Vui Yong Liew , Mikal C. Hunsaker , Michael N. Derr
IPC分类号： G06F5/00
CPC分类号： G06F12/0638
摘要： A system is described for providing a patch mechanism within an input/output (I/O) controller, which can be used to workaround defects and conditions existing in the I/O controller. The system includes a patch module coupled to a completion queue included in the I/O controller. The patch module is used to sample incoming cycles received by the I/O controller and to determine if the captured incoming cycle matches one or more of preprogrammed trigger conditions. The patch module is capable of working around a captured non-posted request cycle by controlling header information loaded into the completion queue and by instructing the completion queue whether or not to discard a completion received from a designated end-device.
摘要翻译：描述了一种系统，用于在输入/输出（I / O）控制器内提供补丁机制，可用于解决I / O控制器中存在的缺陷和状况。该系统包括耦合到包括在I / O控制器中的完成队列的补丁模块。补丁模块用于对I / O控制器接收的进入周期进行采样，并确定捕获的进入周期是否匹配一个或多个预编程触发条件。补丁模块能够通过控制加载到完成队列中的头信息并通过指示完成队列来确定是否丢弃从指定的终端设备接收到的完成，来围绕捕获的非发布请求周期进行操作。

2. 发明授权

US06779062B1 Streamlining ATA device initialization 失效
标题翻译：精简ATA设备初始化
公开(公告)号：US06779062B1
公开(公告)日：2004-08-17
申请号：US09675873
申请日：2000-09-29
申请人： Michael K. Eschmann , Michael N. Derr
发明人： Michael K. Eschmann , Michael N. Derr
IPC分类号： G06F1312
CPC分类号： G06F13/385
摘要： The invention includes a platform having a controller coupled to a central processing unit through a system bus. The platform also includes a register device coupled between the central processing unit and the controller. Moreover, the platform also includes a bus coupled to the controller having an end that is adapted to receive a device. The register device includes a depth that is adapted to hold all instruction packets from the central processing unit without presenting delays due to full conditions.
摘要翻译：本发明包括具有通过系统总线耦合到中央处理单元的控制器的平台。平台还包括耦合在中央处理单元和控制器之间的寄存器。此外，平台还包括耦合到控制器的总线，其具有适于接收设备的端部。寄存器装置包括适于保持来自中央处理单元的所有指令分组的深度，而不会由于全部条件而呈现延迟。

3. 发明授权

US06275887B1 Method and apparatus for terminating a bus transaction if the target is not ready 失效
标题翻译：如果目标未准备就终止总线事务的方法和装置
公开(公告)号：US06275887B1
公开(公告)日：2001-08-14
申请号：US09271616
申请日：1999-03-17
申请人： Michael N. Derr , Robert J. Riesenman
发明人： Michael N. Derr , Robert J. Riesenman
IPC分类号： G06F1336
CPC分类号： G06F13/4226 , G06F13/36
摘要： One embodiment of the present invention is a PCI bus target device. The PCI bus target device includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit is configured to determine whether the PCI bus target device is the target of a first transaction initiated by a first PCI bus master device. The second circuit is configured to determine whether the PCI bus target device is ready to complete the first transaction. The third circuit is configured to determine whether a second PCI bus master device is ready to initiate a second transaction. The fourth circuit is configured to terminate the first transaction if the PCI bus target device is the target of the first transaction and is not ready to complete the first transaction and the second PCI bus master device is ready to initiate the second transaction.
摘要翻译：本发明的一个实施例是PCI总线目标设备。 PCI总线目标器件包括第一电路，第二电路，第三电路和第四电路。第一电路被配置为确定PCI总线目标设备是否是由第一PCI总线主设备发起的第一事务的目标。第二电路被配置为确定PCI总线目标设备是否准备好完成第一次交易。第三电路被配置为确定第二PCI总线主设备是否准备好发起第二事务。第四电路被配置为如果PCI总线目标设备是第一事务的目标并且不准备完成第一事务并且第二PCI总线主设备准备启动第二事务，则终止第一事务。

4. 发明授权

US06775282B1 Bus communication 失效
标题翻译：巴士通讯
公开(公告)号：US06775282B1
公开(公告)日：2004-08-10
申请号：US09472858
申请日：1999-12-27
申请人： Ramamohan R. Vakkalagadda , Venu M. Kuchibhotla , Michael N. Derr
发明人： Ramamohan R. Vakkalagadda , Venu M. Kuchibhotla , Michael N. Derr
IPC分类号： H04L1228
CPC分类号： G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： An apparatus includes at least two circuits having interfaces, for transmitting and receiving bus formatted messages and a port coupled to receive messages from the interfaces. The port broadcasts a first received message that is not destined for one of the circuits to the bus. The port blocks broadcast of a second received message that is destined for one of the circuits to the bus.
摘要翻译：一种装置包括至少两个具有接口的电路，用于发送和接收总线格式化的消息，以及耦合以从接口接收消息的端口。该端口广播第一个接收到的消息，该消息不是去往总线的一个电路。该端口阻止向该总线发送一条电路的第二个接收到的消息的广播。

5. 发明申请

US20190043411A1 VIDEO BANDWIDTH OPTIMIZATION FOR MULTI-MONITOR SYSTEMS 审中-公开
公开(公告)号：US20190043411A1
公开(公告)日：2019-02-07
申请号：US15863396
申请日：2018-01-05
申请人： Prashant D. Chaudhari , Michael N. Derr , Paul Diefenbaugh , Sameer Kalathil Perazhi , Fong-Shek Lam , Arthur Jeremy Runyan , Jason Tanner
发明人： Prashant D. Chaudhari , Michael N. Derr , Paul Diefenbaugh , Sameer Kalathil Perazhi , Fong-Shek Lam , Arthur Jeremy Runyan , Jason Tanner
IPC分类号： G09G3/20 , G06T1/60 , G06F3/14 , G06T9/00
摘要： Various systems and methods for managing graphics subsystems are described herein. A system for managing graphics subsystems of a compute device includes a display controller operable to: receive an indication that a first display of the compute device has been activated; enable a power management feature in a display controller, the power management feature to reduce power consumption of the display controller and associated components, and the power management feature to reduce graphics memory bandwidth usage; receive an indication that a second display has been activated with the first display; and maintain the power management feature for at least the first display.

6. 发明申请

US20140089688A1 Sharing Power Between Domains In A Processor Package 有权
标题翻译：在处理器包中的域间共享电源
公开(公告)号：US20140089688A1
公开(公告)日：2014-03-27
申请号：US13628172
申请日：2012-09-27
申请人： Xiuting C. Man , Avinash N. Ananthakrishnan , Michael N. Derr , Craig Forbell
发明人： Xiuting C. Man , Avinash N. Ananthakrishnan , Michael N. Derr , Craig Forbell
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3206 , Y02D10/126 , Y02D10/16
摘要： In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有至少一个核的第一域以执行指令的处理器，耦合到第一域并具有至少一个非核心电路的第二域和耦合到第一域的功率控制单元（PCU）到第一和第二个域。 PCU可以包括功率共享逻辑以从第二域接收编码的功耗信息，并且至少部分地基于编码的功耗信息来计算第一域的可用功率预算。描述和要求保护其他实施例。

7. 发明授权

US08583948B2 Method, apparatus and system for determining an interface during a power state transition 有权
标题翻译：在功率状态转换期间确定接口的方法，装置和系统
公开(公告)号：US08583948B2
公开(公告)日：2013-11-12
申请号：US13175723
申请日：2011-07-01
申请人： Christopher J. Lake , Michael N. Derr , Bhushan Vaidya , William Knolla , Yitschak Kapschitz , Reuven Rozic
发明人： Christopher J. Lake , Michael N. Derr , Bhushan Vaidya , William Knolla , Yitschak Kapschitz , Reuven Rozic
IPC分类号： G06F1/00 , G06F3/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： Techniques for determining a communication interface of a computer platform. In an embodiment, a power management unit of a computer platform provides to an agent of the platform an indication of a power state. In certain embodiments, the agent determines, based on the indication of the power state, that an interface is expected to be available. The agent may designate information for transmission via the first interface—e.g. in lieu of transmitting the information via a second interface which is available prior to the first interface becoming available.
摘要翻译：用于确定计算机平台通信接口的技术。在一个实施例中，计算机平台的电力管理单元向平台的代理提供电力状态的指示。在某些实施例中，代理基于功率状态的指示来确定接口预期可用。代理可以指定用于经由第一接口进行传输的信息 - 例如，代替通过在第一接口变得可用之前可用的第二接口来发送信息。

8. 发明授权

US07636795B2 Configurable feature selection mechanism 有权
标题翻译：可配置的功能选择机制
公开(公告)号：US07636795B2
公开(公告)日：2009-12-22
申请号：US10883518
申请日：2004-06-30
申请人： Gary M. Hess , Robert W. Strong , Jeffrey T. Brown , Michael N. Derr
发明人： Gary M. Hess , Robert W. Strong , Jeffrey T. Brown , Michael N. Derr
IPC分类号： G06F3/00
CPC分类号： G06F21/71 , G06F21/10 , G06F21/78 , G06F21/82 , G06F2221/2101
摘要： A method, apparatus, and system are disclosed. In one embodiment the method comprises determining whether a feature on a device is permitted to be enabled, determining whether a total number of enabled features on the device is less than or equal to a maximum number of allowable features on the device, and allowing the enabling of the device feature if the device feature is permitted to be enabled and the total number of enabled features on the device is less than or equal to the maximum number of allowable features on the device.
摘要翻译：公开了一种方法，装置和系统。在一个实施例中，该方法包括确定设备上的特征是否被允许被启用，确定设备上的启用特征的总数是否小于或等于设备上允许的特征的最大数目，并允许启用的设备功能，如果允许启用设备功能，并且设备上启用的功能的总数小于或等于设备上允许的功能的最大数量。

9. 发明申请

US20090164819A1 TRI-LAYERED POWER SCHEME FOR ARCHITECTURES WHICH CONTAIN A MICRO-CONTROLLER 有权
标题翻译：用于包含微控制器的架构的三层电源方案
公开(公告)号：US20090164819A1
公开(公告)日：2009-06-25
申请号：US11963215
申请日：2007-12-21
申请人： Michael Berger , Michael N. Derr , Joshua Resch , Mukesh Kataria , Mazen Gedeon , Eli Kupermann , Jeffrey John Vick
发明人： Michael Berger , Michael N. Derr , Joshua Resch , Mukesh Kataria , Mazen Gedeon , Eli Kupermann , Jeffrey John Vick
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152
摘要： Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.
摘要翻译：各种实施例针对包含微控制器的架构的三层电力方案。在一个实施例中，电源管理系统可以包括芯片组中的微控制器，以及用于控制对微控制器的电源的低功耗电力，以及功率控制器以便很好地控制对低功耗电力的供电。电源管理系统可以被布置成在多个功耗状态之间切换。在最大功耗状态下，微控制器打开，电源控制器打开，低功耗电源正常。在中间功耗状态下，微控制器关闭，电源控制器处于打开状态，低功耗电源需要打开。在最小功耗状态下，微控制器处于关闭状态，功率控制器处于开启状态，低功耗状态可以根据电源控制器选择开启或关闭。描述和要求保护其他实施例。

10. 发明授权

US07523327B2 System and method of coherent data transfer during processor idle states 有权
标题翻译：处理器空闲状态期间相干数据传输的系统和方法
公开(公告)号：US07523327B2
公开(公告)日：2009-04-21
申请号：US11074233
申请日：2005-03-05
申请人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
发明人： Leslie E. Cline , Siripong Sritanyaratana , Alon Naveh , Shai Rotem , Eric C. Samson , Michael N. Derr
IPC分类号： G06F1/32
CPC分类号： G06F12/0835 , G06F2212/1028 , Y02D10/13
摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.
摘要翻译：管理电源的系统和方法提供将处理器置于不可窥探状态，其中处理器与系统存储器相关联。当处理器处于非可窥探状态时，可以在控制器和系统存储器之间进行一个或多个数据传输。在一个实施例中，在将处理器置于非可窥探状态之前，确定处理器将处理器的内部高速缓冲器刷新到系统存储器。

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