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1. 发明申请

US20130161643A1 Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces 有权
标题翻译：用平面表面制造三维氮化镓结构的方法
公开(公告)号：US20130161643A1
公开(公告)日：2013-06-27
申请号：US13337843
申请日：2011-12-27
申请人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
发明人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
IPC分类号： H01L33/34 , H01L33/32
CPC分类号： H01L33/34 , H01L33/007 , H01L33/18 , H01L33/24 , H01L33/32
摘要： A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.
摘要翻译：提供了一种用于制造具有平面表面的三维氮化镓（GaN）柱结构的方法。在提供衬底之后，该方法生长覆盖在衬底的顶表面上的GaN膜，并在GaN膜的顶表面中形成空腔。使用激光烧蚀，离子注入，喷砂或干蚀刻工艺形成空腔。然后湿式蚀刻GaN膜顶表面中的空腔，形成延伸到GaN膜中的平面侧壁。更明确地说，空腔形成为c面GaN薄膜顶表面，并且平面侧壁在m平面或a平面系列中垂直于c平面形成。

2. 发明授权

US08685774B2 Method for fabricating three-dimensional gallium nitride structures with planar surfaces 有权
标题翻译：制备具有平面表面的三维氮化镓结构的方法
公开(公告)号：US08685774B2
公开(公告)日：2014-04-01
申请号：US13337843
申请日：2011-12-27
申请人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
发明人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
IPC分类号： H01L21/00
CPC分类号： H01L33/34 , H01L33/007 , H01L33/18 , H01L33/24 , H01L33/32
摘要： A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.
摘要翻译：提供了一种用于制造具有平面表面的三维氮化镓（GaN）柱结构的方法。在提供衬底之后，该方法生长覆盖在衬底的顶表面上的GaN膜，并在GaN膜的顶表面中形成空腔。使用激光烧蚀，离子注入，喷砂或干蚀刻工艺形成空腔。然后湿式蚀刻GaN膜顶表面中的空腔，形成延伸到GaN膜中的平面侧壁。更明确地说，空腔形成为c面GaN薄膜顶表面，并且平面侧壁在m平面或a平面系列中垂直于c平面形成。

3. 发明授权

US08648328B2 Light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces 有权
标题翻译：使用具有平面表面的三维氮化镓（GaN）柱结构的发光二极管（LED）
公开(公告)号：US08648328B2
公开(公告)日：2014-02-11
申请号：US13367120
申请日：2012-02-06
申请人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
发明人： Mark Albert Crowder , Changqing Zhan , Paul J. Schuele
IPC分类号： H01L33/04
CPC分类号： H01L33/32 , H01L33/0075 , H01L33/04 , H01L33/06 , H01L33/08 , H01L33/18 , H01L33/24 , H01L33/42 , H01L2933/0008 , H01L2933/0016
摘要： A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
摘要翻译：提供了一种使用具有平面表面的三维氮化镓（GaN）柱结构来制造发光二极管（LED）的方法。该方法形成多个GaN柱结构，每个GaN柱结构均具有n个掺杂的GaN（n-GaN）柱和垂直于c平面的平面侧壁，形成在m面或平面系列中。形成覆盖在n-GaN支柱侧壁上的多量子阱（MQW）层，并且在MQW层上形成一层p掺杂的GaN（p-GaN）层。多个GaN柱结构沉积在第一衬底上，其中n掺杂的GaN柱侧壁平行于第一衬底的顶表面排列。每个GaN柱结构的第一端连接到第一金属层。蚀刻每个GaN柱结构的第二端以暴露n-GaN柱的第二端并连接到第二金属层。

4. 发明申请

US20120168711A1 Narrow-Waist Nanowire Transistor with Wide Aspect Ratio Ends 审中-公开
标题翻译：具有宽纵横比的窄腰纳米线晶体管
公开(公告)号：US20120168711A1
公开(公告)日：2012-07-05
申请号：US12984641
申请日：2011-01-05
申请人： Mark Albert Crowder , Paul J. Schuele
发明人： Mark Albert Crowder , Paul J. Schuele
IPC分类号： H01L29/08 , H01L21/84 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/122 , H01L29/42392
摘要： A method is provided for forming narrow-waist nanowire (NW) transistors with wide aspect ratio ends. The method provides a semiconductor-on-insulator wafer. The top semiconductor layer is etched to form a first pad, a second pad, and a plurality of narrow-waist semiconductor bridges. Each semiconductor bridge has two ends, each with a first width, attached to the first and second pads, and a mid-section less than the first width. A channel is formed in a center portion of each mid-section, a drain interposed between the channel and the first end, a source interposed between the channel and the second end, and a gate dielectric surrounding the channel and adjacent portions of the source and drain. A gate electrode is formed surrounding the gate dielectric. The semiconductor bridge ends are etched from the first and second pads, forming a plurality of narrow-waist semiconductor NW transistors.
摘要翻译：提供一种用于形成具有宽纵横比端的窄腰纳米线（NW）晶体管的方法。该方法提供绝缘体上半导体晶片。蚀刻顶部半导体层以形成第一焊盘，第二焊盘和多个窄腰半导体桥。每个半导体桥具有两个端部，每个端部具有连接到第一和第二焊盘的第一宽度，以及小于第一宽度的中间部分。在每个中间部分的中心部分形成通道，插入在通道和第一端之间的漏极，介于通道和第二端之间的源极以及围绕通道和源极的相邻部分的栅极电介质，以及排水。围绕栅极电介质形成栅电极。从第一和第二焊盘蚀刻半导体桥端，形成多个窄腰半导体NW晶体管。

5. 发明申请

US20110281368A1 NANOPARTICLE DERIVATIZATION OF TARGETS FOR DETECTING AND DETERMINING THE CONCENTRATIONS OF TARGETS BY IMPEADANCE-SPECTROSCOPY-BASED SENSORS 审中-公开
标题翻译：用于通过基于光谱法的传感器检测和确定目标浓度的目标的纳米颗粒衍生物
公开(公告)号：US20110281368A1
公开(公告)日：2011-11-17
申请号：US12780270
申请日：2010-05-14
申请人： Andrei L. Gindilis , Kevin Robert Schwarzkopf , Paul J. Schuele , Mark Albert Crowder
发明人： Andrei L. Gindilis , Kevin Robert Schwarzkopf , Paul J. Schuele , Mark Albert Crowder
IPC分类号： G01N33/48 , G01N27/00
CPC分类号： G01N27/3278 , Y10T436/143333
摘要： Embodiments of the present invention are directed to for detecting the presence and concentration of one or more particular target molecules in solutions, air or other gasses, or otherwise present in an environment or sample, by impedance-spectroscopy-based sensors. Various embodiments of the present invention provide for derivatizing target molecules with nanoparticles to increase capacitance changes at electrode surfaces in order to generate stronger signals and improve signal-to-noise ratios of impedance-spectroscopy-based sensors.
摘要翻译：本发明的实施方案涉及通过基于阻抗谱的传感器来检测溶液，空气或其它气体中或者以其它方式存在于环境或样品中的一种或多种特定目标分子的存在和浓度。本发明的各种实施方案提供了用纳米颗粒衍生目标分子以增加电极表面的电容变化，以便产生更强的信号并提高基于阻抗谱的传感器的信噪比。

6. 发明授权

US08053266B2 Piezo-diode cantilever MEMS fabrication method 有权
标题翻译：压电二极管悬臂MEMS制造方法
公开(公告)号：US08053266B2
公开(公告)日：2011-11-08
申请号：US12758879
申请日：2010-04-13
申请人： Changqing Zhan , Paul J. Schuele , John F. Conley, Jr. , John W. Hartzell
发明人： Changqing Zhan , Paul J. Schuele , John F. Conley, Jr. , John W. Hartzell
IPC分类号： H01L21/324 , H01L21/84
CPC分类号： B81B3/0021 , H01L29/868
摘要： A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.
摘要翻译：提供压电薄膜二极管（压电二极管）悬臂微机电系统（MEMS）及相关制造工艺。该方法沉积覆盖在基底上的薄膜。基板可以由玻璃，聚合物，石英，金属箔，Si，蓝宝石，陶瓷或化合物半导体材料制成。非晶硅（a-Si），多晶Si（poly-Si），氧化物，a-SiGe，poly-SiGe，金属，含金属的化合物，氮化物，聚合物，陶瓷膜，磁性膜和化合物半导体材料是一些例子的薄膜材料。悬臂梁由薄膜形成，二极管嵌入悬臂梁。二极管由与悬臂梁共用的薄膜制成。共享的薄膜可以是覆盖悬臂梁顶表面的薄膜，覆盖悬臂梁底表面的薄膜或嵌入在悬臂梁内的薄膜。

7. 发明授权

US07763947B2 Piezo-diode cantilever MEMS 有权
标题翻译：压电二极管悬臂MEMS
公开(公告)号：US07763947B2
公开(公告)日：2010-07-27
申请号：US11717231
申请日：2007-03-13
申请人： Changqing Zhan , Paul J. Schuele , John F. Conley, Jr. , John W. Hartzell
发明人： Changqing Zhan , Paul J. Schuele , John F. Conley, Jr. , John W. Hartzell
IPC分类号： H01L41/113
CPC分类号： B81B3/0021 , H01L29/868
摘要： A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.
摘要翻译：提供压电薄膜二极管（压电二极管）悬臂微机电系统（MEMS）及相关制造工艺。该方法沉积覆盖在基底上的薄膜。基板可以由玻璃，聚合物，石英，金属箔，Si，蓝宝石，陶瓷或化合物半导体材料制成。非晶硅（a-Si），多晶Si（poly-Si），氧化物，a-SiGe，poly-SiGe，金属，含金属的化合物，氮化物，聚合物，陶瓷膜，磁性膜和化合物半导体材料是一些例子的薄膜材料。悬臂梁由薄膜形成，二极管嵌入悬臂梁。二极管由与悬臂梁共用的薄膜制成。共享的薄膜可以是覆盖悬臂梁顶表面的薄膜，覆盖悬臂梁底表面的薄膜或嵌入在悬臂梁内的薄膜。

8. 发明申请

US20100197065A1 Piezo-Diode Cantilever MEMS Fabrication Method 有权
标题翻译：压电二极管悬臂MEMS制造方法
公开(公告)号：US20100197065A1
公开(公告)日：2010-08-05
申请号：US12758879
申请日：2010-04-13
申请人： Changqing Zhan , Paul J. Schuele , John F. Conley, JR. , John W. Hartzell
发明人： Changqing Zhan , Paul J. Schuele , John F. Conley, JR. , John W. Hartzell
IPC分类号： H01L21/329
CPC分类号： B81B3/0021 , H01L29/868
摘要： A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.
摘要翻译：提供压电薄膜二极管（压电二极管）悬臂微机电系统（MEMS）及相关制造工艺。该方法沉积覆盖在基底上的薄膜。基板可以由玻璃，聚合物，石英，金属箔，Si，蓝宝石，陶瓷或化合物半导体材料制成。非晶硅（a-Si），多晶Si（poly-Si），氧化物，a-SiGe，poly-SiGe，金属，含金属的化合物，氮化物，聚合物，陶瓷膜，磁性膜和化合物半导体材料是一些例子的薄膜材料。悬臂梁由薄膜形成，二极管嵌入悬臂梁。二极管由与悬臂梁共用的薄膜制成。共享的薄膜可以是覆盖悬臂梁顶表面的薄膜，覆盖悬臂梁底表面的薄膜或嵌入在悬臂梁内的薄膜。

9. 发明授权

US08236631B2 Four-transistor Schmitt trigger inverter with hysteresis 有权
标题翻译：具有迟滞的四晶体管施密特触发器
公开(公告)号：US08236631B2
公开(公告)日：2012-08-07
申请号：US12644061
申请日：2009-12-22
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

10. 发明授权

US07872309B2 Self-aligned lightly doped drain recessed-gate thin-film transistor 有权
标题翻译：自对准轻掺杂漏极栅极薄膜晶体管
公开(公告)号：US07872309B2
公开(公告)日：2011-01-18
申请号：US12140017
申请日：2008-06-16
申请人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译：提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。沟槽有一个底部和侧壁。在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。替代地，LDD长度与沟槽的深度直接相关。

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