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1. 发明授权

US08236631B2 Four-transistor Schmitt trigger inverter with hysteresis 有权
标题翻译：具有迟滞的四晶体管施密特触发器
公开(公告)号：US08236631B2
公开(公告)日：2012-08-07
申请号：US12644061
申请日：2009-12-22
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

2. 发明授权

US07532187B2 Dual-gate transistor display 有权
标题翻译：双栅晶体管显示
公开(公告)号：US07532187B2
公开(公告)日：2009-05-12
申请号：US11184699
申请日：2005-07-18
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： G09G3/36 , G09G3/32
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.
摘要翻译：提供了双栅极薄膜晶体管（DG-TFT）电压存储电路。电路包括电压存储元件，具有连接到数据线的第一源极/漏极（S / D）的DG-TFT，连接到第一栅极线的顶栅极，连接到电压存储器的第二S / D区域元件和连接到偏置线的底栅。在一个方面，电路还包括具有连接到第一栅极线的输入的电压移位器和用于在偏置线上提供偏置电压的输出。电压存储元件的实例包括电容器，液晶（LC）像素和发光二极管（LED）像素。

3. 发明申请

US20100117704A1 Four-Transistor Schmitt Trigger Inverter with Hysteresis 有权
标题翻译：具有迟滞功能的四晶闸管施密特触发逆变器
公开(公告)号：US20100117704A1
公开(公告)日：2010-05-13
申请号：US12644061
申请日：2009-12-22
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

4. 发明授权

US07659586B2 Inverter with four-transistor Schmitt trigger 有权
标题翻译：具有四晶体管施密特触发器的逆变器
公开(公告)号：US07659586B2
公开(公告)日：2010-02-09
申请号：US12142602
申请日：2008-06-19
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H01L29/76 , H01L21/00
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

5. 发明申请

US20080272816A1 Inverter with Four-Transistor Schmitt Trigger 有权
标题翻译：具有四晶体管施密特触发器的逆变器
公开(公告)号：US20080272816A1
公开(公告)日：2008-11-06
申请号：US12142602
申请日：2008-06-19
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

6. 发明授权

US07407843B2 Four-transistor Schmitt trigger inverter 有权
标题翻译：四晶体管施密特触发器
公开(公告)号：US07407843B2
公开(公告)日：2008-08-05
申请号：US11408220
申请日：2006-04-20
申请人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
发明人： Themistokles Afentakis , Apostolos T. Voutsas , Paul J. Schuele
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译：提供了一个四晶体管施密特触发器。施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极，背栅极和源极/漏极区域。（常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。（传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。

7. 发明授权

US07872309B2 Self-aligned lightly doped drain recessed-gate thin-film transistor 有权
标题翻译：自对准轻掺杂漏极栅极薄膜晶体管
公开(公告)号：US07872309B2
公开(公告)日：2011-01-18
申请号：US12140017
申请日：2008-06-16
申请人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
发明人： Paul J. Schuele , Mark A. Crowder , Apostolos T. Voutsas , Hidayat Kisdarjono
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L29/78621 , H01L29/66621 , H01L29/66757 , H01L29/78627
摘要： A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
摘要翻译：提供了具有自对准轻掺杂漏极（LDD）的凹入栅极薄膜晶体管（RG-TFT）以及相应的制造方法。该方法沉积覆盖衬底的绝缘体并蚀刻绝缘体中的沟槽。沟槽有一个底部和侧壁。在绝缘体和沟槽上形成有源硅（Si）层，在有源Si层上方形成栅极氧化层。然后在沟槽中形成凹陷栅电极。 TFT是掺杂的，并且LDD区域形成在覆盖沟槽侧壁的有源Si层中。 LDD区域具有从沟槽侧壁的顶部延伸到沟槽底部的长度，其掺杂密度响应于LDD长度而减小。替代地，LDD长度与沟槽的深度直接相关。

8. 发明授权

US07238554B2 Simultaneous planar and non-planar thin-film transistor processes 失效
标题翻译：同时平面和非平面薄膜晶体管工艺
公开(公告)号：US07238554B2
公开(公告)日：2007-07-03
申请号：US10985587
申请日：2004-11-09
申请人： Paul J. Schuele , Apostolos T. Voutsas
发明人： Paul J. Schuele , Apostolos T. Voutsas
IPC分类号： H01L21/00
CPC分类号： H01L27/12 , H01L29/78624 , H01L29/78642 , H01L29/78648 , H01L29/78675
摘要： A method is provided for concurrently forming MP-TFTs and P-TFTs. Generally, the method comprises: forming a P-TFT having source/drain (S/D) regions, an intervening channel region, and a gate, all in a first horizontal plane; and simultaneously forming a MP-TFT having a first gate in the first horizontal plane and at least one S/D region in a second horizontal plane, overlying the first horizontal plane. The vertical TFT (V-TFT) is an MP-TFT having vertical first gate sidewalls and a vertical channel region overlying a gate sidewall. The dual-gate TFT (DG-TFT) is an MP-TFT having a bottom gate, first and second S/D regions with top surfaces, an intervening channel region with a top surface, and a second, top gate with a bottom surface, all in a second horizontal plane, overlying the first horizontal plane.
摘要翻译：提供了用于同时形成MP-TFT和P-TFT的方法。通常，该方法包括：在第一水平面中形成具有源极/漏极（S / D）区域，中间沟道区域和栅极的P-TFT; 同时在第一水平面上形成具有第一栅极的MP-TFT和位于第一水平面上的第二水平面中的至少一个S / D区域。垂直TFT（V-TFT）是具有垂直的第一栅极侧壁和覆盖栅极侧壁的垂直沟道区的MP-TFT。双栅极TFT（DG-TFT）是具有底栅，具有顶表面的第一和第二S / D区，具有顶表面的中间沟道区和具有底表面的第二顶栅的MP-TFT 都在第二个水平面上，覆盖着第一个水平面。

9. 发明申请

US20140198072A1 In-Pixel Ultrasonic Touch Sensor for Display Applications 有权
标题翻译：用于显示应用的In-Pixel超声波触摸传感器
公开(公告)号：US20140198072A1
公开(公告)日：2014-07-17
申请号：US13740043
申请日：2013-01-11
申请人： Paul J. Schuele , Themistokles Afentakis , John W. Hartzell
发明人： Paul J. Schuele , Themistokles Afentakis , John W. Hartzell
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0412 , G06F3/043
摘要： A video display is provided with a planar piezoelectric transmitter to transmit ultrasound signals, and a display panel including a plurality of pixels. Each pixel has a data interface to accept a video signal with a variable voltage associated with a range of light intensity values, and to supply a touch signal with a variable voltage derived from a range of reflected ultrasound signal energies. Each pixel is made up of a light device to supply light with an intensity responsive to the video signal voltage, and a storage capacitor to maintain a video signal voltage between refresh cycles. A piezoelectric transducer accepts a reflected ultrasound signal energy and maintains a touch signal voltage between refresh cycles. In one aspect, the storage capacitor and the piezoelectric transducer are the same device. The light device may be a liquid crystal (LC) layer or a light emitting diode.
摘要翻译：视频显示器设置有用于传输超声波信号的平面压电发射器，以及包括多个像素的显示面板。每个像素具有接收具有与一定范围的光强度值相关联的可变电压的视频信号的数据接口，并且提供具有从反射的超声信号能量的范围导出的可变电压的触摸信号。每个像素由光装置组成，以响应于视频信号电压的强度提供光，以及存储电容器，用于在刷新周期之间维持视频信号电压。压电传感器接受反射的超声信号能量并在刷新周期之间保持触摸信号电压。一方面，存储电容器和压电换能器是相同的装置。光装置可以是液晶（LC）层或发光二极管。

10. 发明授权

US08896907B2 Plasmonic reflective display fabricated using anodized aluminum oxide 有权
标题翻译：使用阳极氧化铝制造的等离子体反射显示器
公开(公告)号：US08896907B2
公开(公告)日：2014-11-25
申请号：US13449370
申请日：2012-04-18
申请人： Douglas J. Tweet , Akinori Hashimura , Paul J. Schuele , Apostolos T. Voutsas
发明人： Douglas J. Tweet , Akinori Hashimura , Paul J. Schuele , Apostolos T. Voutsas
IPC分类号： G02B26/00 , G02F1/1335
CPC分类号： G02F1/133553 , G02F1/19 , G02F2201/124 , G02F2203/10
摘要： A method is provided for forming a reflective plasmonic display. The method provides a substrate and deposits a bottom dielectric layer. A conductive film is deposited overlying the bottom dielectric layer. A hard mask is formed with nano-size openings overlying the conductive film. The conductive film is plasma etched via nano-size openings in the hard mask, stopping at the dielectric layer. After removing the hard mask, a conductive film is left with nano-size openings to the dielectric layer. Metal is deposited in the nano-size openings, creating a pattern of metallic nanoparticles overlying the dielectric layer. Then, the conductive film is removed. The hard mask may be formed by conformally depositing an Al film overlying the conductive film and anodizing the Al film, creating a hard mask of porous anodized Al oxide (AAO) film. The porous AAO film may form a short-range hexagonal, and long-range random order hole patterns.
摘要翻译：提供了形成反射等离子体显示器的方法。该方法提供衬底并沉积底部电介质层。沉积覆盖在底部介电层上的导电膜。形成具有覆盖导电膜的纳米尺寸开口的硬掩模。导电膜通过硬掩模中的纳米尺寸开口进行等离子体蚀刻，停留在电介质层。在去除硬掩模之后，导电膜留下具有到介电层的纳米尺寸的开口。金属沉积在纳米尺寸的开口中，形成覆盖在介电层上的金属纳米颗粒图案。然后，去除导电膜。硬掩模可以通过共形沉积覆盖在导电膜上的Al膜并阳极氧化Al膜，形成多孔阳极氧化Al氧化物（AAO）膜的硬掩模来形成。多孔AAO膜可以形成短程六边形和长程随机顺序孔图案。

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