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1. 发明授权

US06678184B2 CAM cell having compare circuit formed over two active regions 有权
标题翻译： CAM单元具有形成在两个有效区域上的比较电路
公开(公告)号：US06678184B2
公开(公告)日：2004-01-13
申请号：US10163848
申请日：2002-06-05
申请人： Mark A. Lysinger , Christophe Frey , Frederic LaLanne
发明人： Mark A. Lysinger , Christophe Frey , Frederic LaLanne
IPC分类号： G11C1500
CPC分类号： G11C15/04
摘要： A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.
摘要翻译：公开了具有用于改善CAM单元和CAM阵列的半导体衬底区域利用率的晶体管的物理实现的内容寻址存储器（CAM）单元。 CAM单元包括第一和第二存储器电路和比较电路。六个晶体管的比较电路形成在两个有源区域上。比较电路和由多晶硅区域形成的第一存储器电路之间的局部互连。比较电路和由多晶硅和导电区域形成的第二存储器电路之间的局部互连。

2. 发明申请

US20080211513A1 INITIATION OF FUSE SENSING CIRCUITRY AND STORAGE OF SENSED FUSE STATUS INFORMATION 审中-公开
标题翻译：保险丝感应电路的启动和感应保险丝状态信息的存储
公开(公告)号：US20080211513A1
公开(公告)日：2008-09-04
申请号：US12028504
申请日：2008-02-08
申请人： Mark A. Lysinger , Naren Sahoo
发明人： Mark A. Lysinger , Naren Sahoo
IPC分类号： H01H85/30
CPC分类号： G11C17/16 , G11C17/18 , H01H85/30
摘要： An integrated circuit includes at least one circuit trimming fuse. A fuse sensor circuit is connected to the trimming fuse and operates in response to a fuse sensing initiation signal to initiate sensing of a state of the trimming fuse and generate an output indicative of the sensed state. A latch circuit, including multiple latch locations, redundantly latches the output indicative of the sensed state. A majority logic state in the latch locations is determined by a polling circuit coupled to the multiple latch locations. The polling circuit outputs that majority logic state as a fuse state output indicative of the sensed state of the fuse. A register in the integrated circuit is loadable with a value. A comparison circuit compares the loaded value in the register to a correct fuseword value and, if there is a match, generates the fuse sensing initiation signal for application to the fuse sensor circuit.
摘要翻译：集成电路包括至少一个电路修整保险丝。保险丝传感器电路连接到微调保险丝并且响应于保险丝感测启动信号而操作以启动对修整熔丝的状态的感测并产生指示感测状态的输出。包括多个锁存位置的锁存电路冗余地锁存指示感测状态的输出。锁存位置中的多数逻辑状态由耦合到多个锁存位置的轮询电路确定。轮询电路将多数逻辑状态输出为指示保险丝的感测状态的保险丝状态输出。集成电路中的寄存器可以加载一个值。比较电路将寄存器中的负载值与正确的母线值进行比较，如果存在匹配，则产生用于熔丝传感器电路的熔丝检测启动信号。

3. 发明授权

US4974241A Counter employing exclusive NOR gate and latches in combination 失效
标题翻译：计数器采用异或门或锁存器组合使用
公开(公告)号：US4974241A
公开(公告)日：1990-11-27
申请号：US332290
申请日：1989-03-31
申请人： David C. McClure , Mark A. Lysinger
发明人： David C. McClure , Mark A. Lysinger
IPC分类号： G06F1/12 , G06F5/12 , G11C7/00 , H04J3/06 , H04L7/00
CPC分类号： H04J3/0626
摘要： The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

4. 发明申请

US20080198679A1 SRAM WITH SWITCHABLE POWER SUPPLY SETS OF VOLTAGES 有权
标题翻译：具有可切换电源电压的SRAM
公开(公告)号：US20080198679A1
公开(公告)日：2008-08-21
申请号：US12030463
申请日：2008-02-13
申请人： Mark A. Lysinger , David C. McClure , Francois Jacquet
发明人： Mark A. Lysinger , David C. McClure , Francois Jacquet
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C11/412 , G11C11/413
摘要： A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is provided to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can comprise a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.
摘要翻译：电路包括具有高电压供应节点和低电压供应节点的存储单元。功率复用电路被提供用于根据小区的当前操作模式选择性地将第一组电压和第二组电压中的一个应用于小区的高电压和低电压供应节点。如果单元处于活动读或写模式，则多路复用电路选择性地将第一组电压施加到高电压和低电压供应节点。相反，如果单元处于待机无读或不写模式，则多路复用电路选择性地将第二组电压施加到高电压和低电压供应节点。第二组电压偏离第一组电压。更具体地，第二组电压中的低电压高于第一组电压中的低电压，并且其中第二组电压中的高电压小于第一组电压中的高电压。单元可以是单元阵列的成员，在这种情况下，根据阵列的主动/待机模式，选择性地施加电压应用于阵列。阵列可以包括包括许多块或部分的整个存储器装置内的块或部分，在这种情况下，根据块/部分本身的主动/待机模式，选择性地施加电压施加到各个块/部分。

5. 发明授权

US5805523A Burst counter circuit and method of operation thereof 失效
标题翻译：突发计数器电路及其操作方法
公开(公告)号：US5805523A
公开(公告)日：1998-09-08
申请号：US825971
申请日：1997-04-04
申请人： Mark A. Lysinger
发明人： Mark A. Lysinger
IPC分类号： G11C11/413 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/41 , G11C8/00
CPC分类号： G11C7/1018
摘要： The decoded address signal is stored in the slave latch. The output of the slave latch is a column select signal. The slave latches are organized in a slave latch circuit which is connected as a counter. Each of the slave latches is treated as a register and four slave latches are combined to permit the sequential addresses selected to be in count up or count down as the slave latch circuit is clocked. In addition, a burst counter control circuit selectively controls the counter to produce a count in an interleaved mode or a count up mode. The least significant bit of the address is stored within the burst control circuit for indicating whether the count should be an up count or a down count when operating in the interleaved mode.
摘要翻译：解码的地址信号被存储在从锁存器中。从锁存器的输出是列选择信号。从锁存器组织在作为计数器连接的从锁存电路中。每个从锁存器被视为寄存器，并且组合四个从锁存器，以允许所选择的顺序地址在从锁存电路被计时时被递增计数或递减计数。此外，突发计数器控制电路选择性地控制计数器以产生交错模式或递增计数模式的计数。地址的最低有效位被存储在突发控制电路内，用于指示当以交织模式操作时计数应该是递增计数还是递减计数。

6. 发明授权

US5450019A Precharging output driver circuit 失效
标题翻译：预充电输出驱动电路
公开(公告)号：US5450019A
公开(公告)日：1995-09-12
申请号：US185650
申请日：1994-01-26
申请人： David C. McClure , Mark A. Lysinger , William C. Slemmer
发明人： David C. McClure , Mark A. Lysinger , William C. Slemmer
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361
摘要： A push-pull output driver circuit is disclosed which includes control circuitry for controlling the gates of the driver transistors to effect precharge of the output terminal at the beginning of a cycle. Precharge is initiated at the beginning of each cycle, for example indicated by an address transition. The prior data state at the output is stored, and enables the opposing driver transistor from that which drove the stored prior data state by enabling a gated level detector with hysteresis, such as a Schmitt trigger, associated therewith. The transistor that drove the stored prior data state is disabled, thus precluding oscillations during precharge. The gated Schmitt triggers each receive the voltage of the output terminal and, when enabled, turn on a transistor which couples the output terminal to the gate of the driver transistor. The Schmitt triggers also control the precharge to terminate when the output terminal has reached an intermediate voltage, and so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to the gate of the precharging driver transistor helps to eliminate overshoot during precharge.
摘要翻译：公开了一种推挽输出驱动器电路，其包括用于控制驱动器晶体管的栅极以在周期开始时实现输出端子的预充电的控制电路。预充电在每个周期开始时启动，例如由地址转换指示。存储输出端的先前数据状态，并且通过启用具有滞后的门控电平检测器（例如施密特触发器）来驱动存储的先前数据状态的驱动晶体管，使相对的驱动器晶体管成为可能。驱动存储的先前数据状态的晶体管被禁用，从而排除了预充电期间的振荡。门控施密特触发器每个接收输出端子的电压，并且在使能时，接通将输出端子耦合到驱动晶体管的栅极的晶体管。当输出端子达到中间电压时，施密特触发器也可以控制预充电，从而由于滞后特性使振荡最小化。输出端子连接到预充电驱动晶体管的栅极有助于在预充电期间消除过冲。

7. 发明申请

US20080198678A1 PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES 有权
标题翻译：可编程SRAM SRAM源开发方案可供选择的SRAM供电电压组
公开(公告)号：US20080198678A1
公开(公告)日：2008-08-21
申请号：US12029366
申请日：2008-02-11
申请人： David C. McClure , Mark A. Lysinger , Mehdi Zamanian , Francois Jacquet , Philippe Roche
发明人： David C. McClure , Mark A. Lysinger , Mehdi Zamanian , Francois Jacquet , Philippe Roche
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C5/148 , G11C11/41 , G11C11/413 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.
摘要翻译：存储电路具有高电压和低电压电源节点。根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。如果处于主动读/写模式，则选择性地施加第一组电压。相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压所述第一组电压通过多个高偏移电压中的所选择的一个。偏移电压由选择性有效的基于二极管的电路提供。选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

8. 发明授权

US5784331A Multiple access memory device 失效
标题翻译：多路存取存储器
公开(公告)号：US5784331A
公开(公告)日：1998-07-21
申请号：US775664
申请日：1996-12-31
申请人： Mark A. Lysinger
发明人： Mark A. Lysinger
IPC分类号： G06F12/06 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1018 , G11C7/103 , G11C7/1033 , G11C7/1072
摘要： A memory circuit has a plurality of data storage locations and an address associated with each data storage location. A first decoded address storage circuit stores a first decoded memory address and outputs the stored first decoded memory address. A second decoded address storage circuit stores a second decoded memory address and outputs the stored second decoded memory address. An address access circuit is coupled to the output of the first decoded address storage circuit and accesses the data storage location associated with the first decoded memory address in response to the first decoded memory address being output from the first decoded address storage circuit. A control circuit is coupled to the first decoded address storage circuit for controlling the transfer of decoded memory address information from the second decoded address storage circuit to the first decoded address storage circuit.
摘要翻译：存储器电路具有多个数据存储位置和与每个数据存储位置相关联的地址。第一解码地址存储电路存储第一解码存储器地址并输出存储的第一解码存储器地址。第二解码地址存储电路存储第二解码存储器地址并输出存储的第二解码存储器地址。响应于从第一解码地址存储电路输出的第一解码存储器地址，地址访问电路耦合到第一解码地址存储电路的输出，并访问与第一解码存储器地址相关联的数据存储位置。控制电路耦合到第一解码地址存储电路，用于控制解码的存储器地址信息从第二解码地址存储电路传送到第一解码地址存储电路。

9. 发明授权

US5608678A Column redundancy of a multiple block memory architecture 失效
标题翻译：多块存储器架构的列冗余
公开(公告)号：US5608678A
公开(公告)日：1997-03-04
申请号：US509351
申请日：1995-07-31
申请人： Mark A. Lysinger
发明人： Mark A. Lysinger
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/808
摘要： According to the present invention, column redundancy circuitry provides column redundancy to an integrated circuit memory device having a multiple block memory architecture with limited programming overhead and maximum flexibility. Column redundancy circuitry is placed within a block of the multiple block memory architecture and may be placed within multiple blocks of the integrated circuit device as required. The column redundancy circuitry has a column select multiplexing circuit, an input/output select circuit for a redundant column of the memory array, and a redundant column select circuit to drive the input/output select circuit for a redundant column. Fuse circuitry contained within column select multiplexing circuit disables a bad prime column by removing fuses in order to isolate the bitline pair associated with the bad column from the read and write busses of the memory array. A fuse of an input/output select circuit contained within an input/output group of a block containing the redundant column to be enabled is left intact in order to connect the bitline pair of the enabled redundant column to the read and write busses of the memory array. The fuses of other input/output select circuits contained within the remaining input/output groups of the block are removed in order to isolate the redundant column from the write and read busses of the other input/output groups. The state of a redundant column signal of the input/output select circuit and whether the fuse is intact or removed will determine whether a redundant column is accessed. Control of the redundant column signal is provided by the redundant column select circuit; thus the redundant column select circuit drives the input/output select circuit for a redundant column.
摘要翻译：根据本发明，列冗余电路为具有具有有限编程开销和最大灵活性的多块存储器架构的集成电路存储器件提供列冗余。列冗余电路放置在多块存储器架构的块内，并且可以根据需要放置在集成电路器件的多个块内。列冗余电路具有列选择多路复用电路，用于存储器阵列的冗余列的输入/输出选择电路和用于驱动冗余列的输入/输出选择电路的冗余列选择电路。包含在列选择复用电路中的保险丝电路通过去除保险丝来禁用不良主列，以便将与坏列相关联的位线对与存储器阵列的读和写总线隔离。包含在包含要使能的冗余列的块的输入/输出组内的输入/输出选择电路的保险丝保持原样，以便将启用冗余列的位线对连接到存储器的读和写总线数组。除去块中剩余输入/输出组内的其他输入/输出选择电路的熔丝，以将冗余列与其他输入/输出组的写入和读出总线隔离开。输入/输出选择电路的冗余列信号的状态以及熔丝是否完整或被去除将决定是否访问冗余列。冗余列信号的控制由冗余列选择电路提供; 冗余列选择电路驱动冗余列的输入/输出选择电路。

10. 发明授权

US5267210A SRAM with flash clear for selectable I/OS 失效
标题翻译：具有闪存的SRAM可选I / OS
公开(公告)号：US5267210A
公开(公告)日：1993-11-30
申请号：US25894
申请日：1993-03-03
申请人： David C. McClure , Mark A. Lysinger
发明人： David C. McClure , Mark A. Lysinger
IPC分类号： G11C7/10 , G11C7/12 , G11C7/20 , G11C11/412 , G11C11/40
CPC分类号： G11C11/412 , G11C7/1048 , G11C7/12 , G11C7/20
摘要： A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.
摘要翻译：具有多个I / O的静态随机存取存储器包括存储器单元（42）的存储器阵列（10），所述存储器单元（42）具有作为相关I / O的函数可选择地清零的列。这些列以成对（34）排列，成对（34）中的每个列与相同的I / O相关联。在线路（28）上输入清除信号并由驱动器（30）驱动。清除信号仅与与选择的I / O相关联的对（34）相关联。与未选择的I / O相关联的其余存储单元列不会被清除。

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