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1. 发明申请

US20080198678A1 PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES 有权
标题翻译：可编程SRAM SRAM源开发方案可供选择的SRAM供电电压组
公开(公告)号：US20080198678A1
公开(公告)日：2008-08-21
申请号：US12029366
申请日：2008-02-11
申请人： David C. McClure , Mark A. Lysinger , Mehdi Zamanian , Francois Jacquet , Philippe Roche
发明人： David C. McClure , Mark A. Lysinger , Mehdi Zamanian , Francois Jacquet , Philippe Roche
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C5/148 , G11C11/41 , G11C11/413 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.
摘要翻译：存储电路具有高电压和低电压电源节点。根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。如果处于主动读/写模式，则选择性地施加第一组电压。相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压所述第一组电压通过多个高偏移电压中的所选择的一个。偏移电压由选择性有效的基于二极管的电路提供。选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

2. 发明授权

US07688669B2 Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages 有权
标题翻译：可编程SRAM源偏置方案，用于可切换SRAM电源组的电压
公开(公告)号：US07688669B2
公开(公告)日：2010-03-30
申请号：US12029366
申请日：2008-02-11
申请人： David C. McClure , Mark A. Lysinger , Mehdi Zamanian , François Jacquet , Philippe Roche
发明人： David C. McClure , Mark A. Lysinger , Mehdi Zamanian , François Jacquet , Philippe Roche
IPC分类号： G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C5/148 , G11C11/41 , G11C11/413 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.
摘要翻译：存储电路具有高电压和低电压电源节点。根据存储器操作模式，第一和第二组电压中的一个选择性地施加到存储器电路的供电节点。如果处于主动读/写模式，则选择性地施加第一组电压。相反，如果在备用无读/无写模式下，则选择性地施加第二组电压。所述第二组电压中的低电压大于所述第一组电压中的低电压，所述第一组电压中的低电压通过多个低失调电压中的所选择的一个，并且所述第二组电压中的高电压小于所述第二组电压中的高电压所述第一组电压通过多个高偏移电压中的所选择的一个。偏移电压由选择性有效的基于二极管的电路提供。选择性激活由可选择地可熔断的熔丝元件或选择性激活的开关元件提供。

3. 发明申请

US20090196085A1 SRAM MEMORY CELL PROTECTED AGAINST CURRENT OR VOLTAGE SPIKES 有权
标题翻译： SRAM存储单元保护电流或电压SPIKES
公开(公告)号：US20090196085A1
公开(公告)日：2009-08-06
申请号：US12421821
申请日：2009-04-10
申请人： Philippe Roche , Francois Jacquet
发明人： Philippe Roche , Francois Jacquet
IPC分类号： G11C5/02 , H01L23/62 , H01L29/66 , G11C5/14 , G11C5/06 , G11C11/00
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.
摘要翻译：存储器单元被保护以防止电流或电压尖峰。小区包括用于在至少一对互补节点中存储信息的一组冗余数据存储节点。小区还包括用于在当前或电压尖峰之后将信息恢复到其初始状态的电路，其使用存储在另一节点中的信息来修改对中的一个节点中的信息。单元中每对的数据存储节点在限定存储单元的边界的衬底的区域内相互注入相对导电类型的相对侧。

4. 发明授权

US07872894B2 SRAM memory cell protected against current or voltage spikes 有权
标题翻译： SRAM存储单元保护电流或电压尖峰
公开(公告)号：US07872894B2
公开(公告)日：2011-01-18
申请号：US12421821
申请日：2009-04-10
申请人： Philippe Roche , Francois Jacquet
发明人： Philippe Roche , Francois Jacquet
IPC分类号： G11C5/06
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.
摘要翻译：存储器单元被保护以防止电流或电压尖峰。小区包括用于在至少一对互补节点中存储信息的一组冗余数据存储节点。小区还包括用于在当前或电压尖峰之后将信息恢复到其初始状态的电路，其使用存储在另一节点中的信息来修改对中的一个节点中的信息。单元中每对的数据存储节点在限定存储单元的边界的衬底的区域内相互注入相对导电类型的相对侧。

5. 发明申请

US20080049524A1 LOGIC CELL PROTECTED AGAINST RANDOM EVENTS 有权
标题翻译：逻辑单元保护反对随机事件
公开(公告)号：US20080049524A1
公开(公告)日：2008-02-28
申请号：US11844025
申请日：2007-08-23
申请人： Gilles Gasiot , Francois Jacquet , Philippe Roche
发明人： Gilles Gasiot , Francois Jacquet , Philippe Roche
IPC分类号： G11C7/00
CPC分类号： G11C11/4125
摘要： A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.
摘要翻译：存储器单元以彼此互补的第一逻辑电平和第二逻辑电平的形式存储信息。存储单元包括用于存储第一逻辑电平和第二逻辑电平的第一存储电路和第二存储电路。第一和第二存储电路各自具有相应的输入和输出。除了在访问第一和第二存储电路期间，隔离电路提供第一存储装置的输入与第二存储装置的输出的电隔离。

6. 发明申请

US20070216464A1 Circuit for distributing an initial signal with a tree structure, protected against logic random events 有权
标题翻译：用于分配具有树结构的初始信号的电路，防止逻辑随机事件
公开(公告)号：US20070216464A1
公开(公告)日：2007-09-20
申请号：US11713469
申请日：2007-03-01
申请人： Philippe Roche , Francois Jacquet , Jean-Jacques De Jong
发明人： Philippe Roche , Francois Jacquet , Jean-Jacques De Jong
IPC分类号： G06F1/04
CPC分类号： H03K19/00338 , G06F1/10 , G06F1/24 , H03K5/1506
摘要： An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.
摘要翻译：本发明的一个实施例涉及一种用于分发初始信号的电路，包括接收初始信号的输入节点，每个向电路组件提供至少一个结果信号的多个终端节点，以及输入节点和连接多个中间节点的多个终端节点，其中连接分支被复制，使得输入节点和中间节点之间的每个节点包括两个输入和两个输出，允许初始信号向终端双重传播节点通过重复连接分支，每个终端节点终端节点接收两个输入信号，初始信号的图像并提供所得到的初始信号：如果所述输入信号相同或不活动，则输入信号的图像如果输入信号不同从彼此。

7. 发明申请

US20060056230A1 Implementation of a multivibrator protected against current or voltage spikes 有权
标题翻译：实现多谐振荡器防止电流或电压尖峰
公开(公告)号：US20060056230A1
公开(公告)日：2006-03-16
申请号：US11225887
申请日：2005-09-12
申请人： Francois Jacquet , Philippe Roche
发明人： Francois Jacquet , Philippe Roche
IPC分类号： G11C7/10 , G11C11/00
CPC分类号： H03K3/35625 , H03K3/0375 , H03K3/356156
摘要： A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes for storing information in at least one pair of complementary nodes and circuitry for restoring information in its initial state, after a current or voltage spike has modified the information in one of the nodes of the said pair, on the basis of the information stored in the other node. The nodes of each pair are implanted opposite one another in a zone of a substrate defining the latch cell.
摘要翻译：多谐振荡器包括接收多谐振荡器输入数据作为输入的第一数据传送端口。第一个主锁存单元连接在第一个传输端口的输出侧。第二个从锁存单元通过位于第一和第二锁存单元之间的第二数据传送端口连接到其上。每个锁存单元包括一组用于在至少一对互补节点中存储信息的冗余数据存储节点和用于在其初始状态中恢复信息的电路，在电流或电压尖峰已经修改了所述第一个节点中的一个节点中的信息对，基于存储在另一个节点中的信息。每对的节点在限定锁存单元的衬底的区域中彼此相对植入。

8. 发明授权

US07741877B2 Circuit for distributing an initial signal with a tree structure, protected against logic random events 有权
标题翻译：用于分配具有树结构的初始信号的电路，防止逻辑随机事件
公开(公告)号：US07741877B2
公开(公告)日：2010-06-22
申请号：US11713469
申请日：2007-03-01
申请人： Philippe Roche , Francois Jacquet , Jean-Jacques De Jong
发明人： Philippe Roche , Francois Jacquet , Jean-Jacques De Jong
IPC分类号： H03K19/00 , G06F1/04
CPC分类号： H03K19/00338 , G06F1/10 , G06F1/24 , H03K5/1506
摘要： An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal: an image of the input signals if said input signals are identical, or inactive, if the input signals are different from each other.
摘要翻译：本发明的一个实施例涉及一种用于分发初始信号的电路，包括接收初始信号的输入节点，每个向电路组件提供至少一个结果信号的多个终端节点，以及输入节点和连接多个中间节点的多个终端节点，其中连接分支被复制，使得输入节点和中间节点之间的每个节点包括两个输入和两个输出，允许初始信号向终端双重传播节点通过重复连接分支，每个终端节点终端节点接收两个输入信号，初始信号的图像并提供所得到的初始信号：如果所述输入信号相同或不活动，则输入信号的图像如果输入信号不同从彼此。

9. 发明授权

US07321506B2 Multivibrator protected against current or voltage spikes 有权
标题翻译：多谐振荡器可防止电流或电压尖峰
公开(公告)号：US07321506B2
公开(公告)日：2008-01-22
申请号：US11379720
申请日：2006-04-21
申请人： Philippe Roche , Francois Jacquet , Sylvain Clerc
发明人： Philippe Roche , Francois Jacquet , Sylvain Clerc
IPC分类号： G11C11/41
CPC分类号： H03K3/02335 , H03K3/0375
摘要： The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.
摘要翻译：多谐振荡器被保护以防止电流或电压尖峰，并且包括第一数据传输端口，其接收作为输入的多谐振荡器输入数据，以及连接在第一传输端口的输出侧的第一/主机锁存单元。包括第二/从属锁存单元，并且第二数据传送端口被放置在第一和第二锁存单元之间。每个锁存单元包含一组冗余数据存储节点。传输端口每个电路/用于将数据单独写入每个存储节点的设备。

10. 发明授权

US07236031B2 Fast bistable circuit protected against random events 有权
标题翻译：快速双稳态电路可防止随机事件
公开(公告)号：US07236031B2
公开(公告)日：2007-06-26
申请号：US11159818
申请日：2005-06-23
申请人： Sylvain Clerc , Philippe Roche , Francois Jacquet
发明人： Sylvain Clerc , Philippe Roche , Francois Jacquet
IPC分类号： H03K3/356
CPC分类号： H03K3/0375
摘要： A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.
摘要翻译：双稳态电路包括具有耦合到第一反相器的输出的一个输入的第一反相器和电容反相电路。电容反相电路包括并联到输入端的电容反相电路和电容性反相电路的输出的第二反相器和电容电路。双稳态电路还包括开关，当开关接收到有效验证信号时或者如果不是将电容性反转电路的输出耦合到第一反相器的输入端，则将电容反转电路的输出与第一反相器的输入隔离第一台逆变器

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