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1. 发明授权

US07218628B2 Method and device for detecting preamble of wireless data frame 有权
标题翻译：用于检测无线数据帧前导码的方法和装置
公开(公告)号：US07218628B2
公开(公告)日：2007-05-15
申请号：US10209489
申请日：2002-07-29
申请人： Mao-Ching Chiu , Chu-Ming Lin , Po-Hung Chen , Chin-Wen Lin , Tai-Yuan Cheng
发明人： Mao-Ching Chiu , Chu-Ming Lin , Po-Hung Chen , Chin-Wen Lin , Tai-Yuan Cheng
IPC分类号： H04J3/24
CPC分类号： H04W99/00 , H04L7/042
摘要： A method and a device for detecting a preamble type of a wireless data frame are provided. The preamble has a synchronization (SYNC) field and a start frame delimiter (SFD) field, and the method comprises following steps. The wireless data frame is first received, and then determined whether the wireless data frame has a short preamble. When the wireless data frame has the short preamble, the wireless data frame is transmitted to a MAC device. In addition, if the wireless data frame does not have the short preamble, it determines whether the wireless data frame has a long preamble. When the wireless data frame has the long preamble, the wireless data frame is then transmitted to the MAC device.
摘要翻译：提供了一种用于检测无线数据帧的前同步码类型的方法和装置。前导码具有同步（SYNC）字段和起始帧分隔符（SFD）字段，并且该方法包括以下步骤。首先接收无线数据帧，然后确定无线数据帧是否具有短前导码。当无线数据帧具有短前导码时，无线数据帧被发送到MAC设备。此外，如果无线数据帧不具有短前导码，则它确定无线数据帧是否具有长前导码。当无线数据帧具有长的前导码时，无线数据帧然后被发送到MAC设备。

2. 发明授权

US08194490B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
申请人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Po-Hung Chen , Chin-Huang Wang , Yen-Chieh Huang , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译：一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

3. 发明申请

US20090141573A1 System and Method for Better Testability of OTP Memory 有权
标题翻译： OTP内存的可测试性的系统和方法
公开(公告)号：US20090141573A1
公开(公告)日：2009-06-04
申请号：US12124989
申请日：2008-05-21
申请人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

4. 发明授权

US07405456B2 Optical sensor chip package 失效
标题翻译：光传感器芯片封装
公开(公告)号：US07405456B2
公开(公告)日：2008-07-29
申请号：US11225077
申请日：2005-09-14
申请人： Po-Hung Chen , Chin-Cheng Lo , Mao-Jung Chen
发明人： Po-Hung Chen , Chin-Cheng Lo , Mao-Jung Chen
IPC分类号： H01L29/40
CPC分类号： H01L27/14618 , H01L27/14625 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an optical sensor chip package in a cavity of forming frame thereof and has a gap between protection layer and optical sensor chip. The optical sensor chip avoids accepting the pressure from protection layer that damage the reliability between pads and metallic traces when protection layer lay on the forming frame. It improves drawbacks of the glue pass trough the gap between optical sensor chip and pads into the optical sensor area of optical sensor chip. It improves the high process yield and reduces the height of optical sensor chip package to achieve lightly and thinly.
摘要翻译：本发明涉及其形成框架的空腔中的光学传感器芯片封装，并且在保护层和光学传感器芯片之间具有间隙。当保护层位于成型框架上时，光学传感器芯片避免接受来自保护层的压力，从而损坏焊盘和金属迹线之间的可靠性。它改善了光学传感器芯片和焊盘之间的间隙的胶合通过光学传感器芯片的光学传感器区域的缺点。它提高了高工艺成品率，降低了光学传感器芯片封装的高度，实现轻薄。

5. 发明申请

US20070090478A1 Image sensor package structure 审中-公开
标题翻译：图像传感器封装结构
公开(公告)号：US20070090478A1
公开(公告)日：2007-04-26
申请号：US11251777
申请日：2005-10-18
申请人： Po-Hung Chen , Mao-Jung Chen
发明人： Po-Hung Chen , Mao-Jung Chen
IPC分类号： H01L31/0203
CPC分类号： H01L27/14618 , H01L27/14683 , H01L31/0203 , H01L2924/0002 , H01L2924/00
摘要： An image sensor package structure is proposed, in which an image sensor is fixed on a substrate having metallization traces and an adhesion layer. Electric paths of the package structure are changed from the COG (chip on glass) process to the CIS (CMOS image sensor) process to improve electric characteristics. Moreover, spacers are formed at appropriate positions to prevent glue overflow from contaminating the sensing regions and solder balls. The proposed package structure can also shrink the package area to greatly enhance the yield and quality.
摘要翻译：提出了一种图像传感器封装结构，其中图像传感器固定在具有金属化迹线和粘合层的基板上。封装结构的电气路径从COG（玻璃上芯片）工艺转变为CIS（CMOS图像传感器）工艺，以改善电气特性。而且，在适当的位置形成间隔物，以防止胶水溢出污染感测区域和焊球。提出的包装结构也可以缩小包装面积，大大提高产量和质量。

6. 发明申请

US20190123476A1 CONNECTOR WITH LATCH PROTECTION 审中-公开
公开(公告)号：US20190123476A1
公开(公告)日：2019-04-25
申请号：US16124200
申请日：2018-09-07
申请人： Po-Hung Chen
发明人： Po-Hung Chen
IPC分类号： H01R13/506 , H01R12/71 , H01R13/405 , H01R13/6585
CPC分类号： H01R13/506 , H01R12/716 , H01R13/405 , H01R13/6275 , H01R13/6583 , H01R13/6585 , H01R24/60 , H01R2107/00
摘要： A connector with latch protection includes a metal casing, an insulating body, plural metal terminals and a partition. The insulating body covers the interior of the metal casing and has a tab extended forwardly from the front of the insulating body and disposed apart on the top and bottom of the tab respectively, and both sides of the tab corresponding to a connecting plug form an inwardly concave portion, and both sides of the partition have a protection plate corresponding to each inwardly concave portion and the front of the tab and bent and extended forwardly. When the partition is embedded into the insulating body by a molding method, a portion of the two metal protection plates exposed from the tab forms a pair of latch grooves for latching the connecting plug to effectively improve the durability and life and lower the manufacturing cost of the connector significantly.

7. 发明授权

US09000751B2 Voltage detecting circuit 有权
标题翻译：电压检测电路
公开(公告)号：US09000751B2
公开(公告)日：2015-04-07
申请号：US13396235
申请日：2012-02-14
申请人： Po-Hung Chen , Makoto Takamiya , Takayasu Sakurai
发明人： Po-Hung Chen , Makoto Takamiya , Takayasu Sakurai
IPC分类号： G01R1/30 , G01R19/165 , G01F3/20
CPC分类号： G01R19/16519 , G01F3/20
摘要： In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.
摘要翻译：在电压检测电路中，晶体管被配置为P型MOSFET，并且包括与输入端连接的源极，与接地电压端子连接的栅极和与输出端子连接的漏极。晶体管被配置为P型MOSFET，并且包括与输出端连接的栅极和源极以及与接地端子连接的漏极。调节晶体管的栅极宽度和栅极长度，并调整晶体管的栅极宽度和栅极长度，使得在晶体管的源极和漏极之间流动的源极 - 漏极电流变得等于在源极和漏极之间流动的源极 - 漏极电流当施加到输入端子的电压被设置为预置触发电压时，晶体管。该配置通过简单的配置实现了输入电压超过触发电压的检测。

8. 发明授权

US08427857B2 Electrical fuse programming time control scheme 有权
标题翻译：电熔丝编程时间控制方案
公开(公告)号：US08427857B2
公开(公告)日：2013-04-23
申请号：US12774851
申请日：2010-05-06
申请人： Po-Hung Chen , Sung-Chieh Lin , Kuoyuan Hsu , Jiann-Tseng Huang
发明人： Po-Hung Chen , Sung-Chieh Lin , Kuoyuan Hsu , Jiann-Tseng Huang
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
摘要翻译：电路包括熔丝和感测和控制电路。熔丝耦合在MOS晶体管和电流源节点之间。感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

9. 发明申请

US20100066944A1 Display Device with Low Scratch Visibility and Manufacturing Method Thereof 有权
标题翻译：具有低刮痕可见性的显示装置及其制造方法
公开(公告)号：US20100066944A1
公开(公告)日：2010-03-18
申请号：US12544813
申请日：2009-08-20
申请人： Kuang-Hua Mei , Shih-Ping Lin , Po-Hung Chen
发明人： Kuang-Hua Mei , Shih-Ping Lin , Po-Hung Chen
IPC分类号： G02F1/13357 , G09F13/04 , H01J9/20
CPC分类号： G02B6/0053 , G02B5/0231 , G02B5/0278
摘要： A display device and a manufacturing method thereof are provided. The display device includes a light guide, a light source, and a brightness enhancement film (BEF), and a dual brightness enhancement film (DBEF). The light guide has a first edge along a first direction and a second edge adjacent to the first edge corresponding to the light source. The BEF is disposed on the light guide and has a plurality of prisms along a second direction which rotates from 0 to 90 degrees with respect to the first direction. The DBEF has a transmission axis along a third direction which also rotates from 0 to 90 degrees with respect to the first direction.
摘要翻译：提供了显示装置及其制造方法。显示装置包括光导，光源和亮度增强膜（BEF）和双亮度增强膜（DBEF）。光导具有沿着第一方向的第一边缘和与对应于光源的第一边缘相邻的第二边缘。 BEF设置在光导上，并且沿着相对于第一方向从0转到90度的第二方向具有多个棱镜。 DBEF具有沿着第三方向的传动轴，其相对于第一方向也从0转到90度。

10. 发明申请

US20080238439A1 Methods of testing fuse elements for memory devices 失效
标题翻译：测试存储器件熔丝元件的方法
公开(公告)号：US20080238439A1
公开(公告)日：2008-10-02
申请号：US11731960
申请日：2007-04-02
申请人： Sung-Chieh Lin , Po-Hung Chen
发明人： Sung-Chieh Lin , Po-Hung Chen
IPC分类号： G01R31/327
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027
摘要： A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element.
摘要翻译：提供一种测试用于存储器件的熔丝元件的方法。第一测试探针电连接到存储器件的程序终端。第二测试探针电连接到接地端子。保险丝元件位于程序端子和接地端子之间的电路上。第一和第二测试探针电连接到测试装置。测试设备在程序终端和接地端子之间施加第一个电压。第一电压的第一电流的至少一部分流过熔丝元件。在熔断元件上流动的第一电流和第一电流的至少一部分不足以改变熔丝元件的导电状态。测量第一电流并用于评估熔丝元件的导电状态。

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