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1. 发明申请

US20120212080A1 PERMANENT MAGNET MOTOR 有权
标题翻译：永磁电机
公开(公告)号：US20120212080A1
公开(公告)日：2012-08-23
申请号：US13399647
申请日：2012-02-17
申请人： Mao Xiong Jiang , Yue Li , Jian Zhao , Hong Min Wei , Ke Lin Zhou , Xing Zhang
发明人： Mao Xiong Jiang , Yue Li , Jian Zhao , Hong Min Wei , Ke Lin Zhou , Xing Zhang
IPC分类号： H02K23/04 , H02K7/08 , H02K7/116 , H02K1/17
CPC分类号： H02K5/148 , H02K5/24 , H02K7/1166 , H02K13/006
摘要： A permanent magnet motor has a rotor and a stator. The rotor has a shaft, a rotor core and commutator fixed to the shaft, and rotor windings wound about poles of the rotor core and electrically connected to the commutator. The stator has an axially extending round housing, a ring magnet member fixed to an inner surface of the round housing, an endcap, and at least one pair of brushes in sliding contact with the commutator. A chamber is formed by the housing and the endcap. The commutator is disposed in the chamber. A window lift device incorporating the motor is also provided.
摘要翻译：永磁电动机具有转子和定子。转子具有轴，转子芯和固定到轴的换向器，转子绕组缠绕在转子芯的极上并电连接到换向器。定子具有轴向延伸的圆形壳体，固定到圆形壳体的内表面的环形磁体构件，端盖以及与换向器滑动接触的至少一对电刷。一个室由壳体和端盖形成。换向器设置在腔室中。还提供了结合电动机的窗户提升装置。

2. 发明授权

US09124152B2 Permanent magnet motor 有权
标题翻译：永磁电机
公开(公告)号：US09124152B2
公开(公告)日：2015-09-01
申请号：US13399647
申请日：2012-02-17
申请人： Mao Xiong Jiang , Yue Li , Jian Zhao , Hong Min Wei , Ke Lin Zhou , Xing Zhang
发明人： Mao Xiong Jiang , Yue Li , Jian Zhao , Hong Min Wei , Ke Lin Zhou , Xing Zhang
IPC分类号： H02K23/04 , H02K5/14 , H02K5/24 , H02K7/116 , H02K13/00
CPC分类号： H02K5/148 , H02K5/24 , H02K7/1166 , H02K13/006
摘要： A permanent magnet motor has a rotor and a stator. The rotor has a shaft, a rotor core and commutator fixed to the shaft, and rotor windings wound about poles of the rotor core and electrically connected to the commutator. The stator has an axially extending round housing, a ring magnet member fixed to an inner surface of the round housing, an endcap, and at least one pair of brushes in sliding contact with the commutator. A chamber is formed by the housing and the endcap. The commutator is disposed in the chamber. A window lift device incorporating the motor is also provided.
摘要翻译：永磁电动机具有转子和定子。转子具有轴，转子芯和固定到轴的换向器，转子绕组缠绕在转子芯的极上并电连接到换向器。定子具有轴向延伸的圆形壳体，固定到圆形壳体的内表面的环形磁体构件，端盖以及与换向器滑动接触的至少一对电刷。一个室由壳体和端盖形成。换向器设置在腔室中。还提供了结合电动机的窗户提升装置。

3. 发明授权

US08673722B2 Strained channel field effect transistor and the method for fabricating the same 有权
标题翻译：应变通道场效应晶体管及其制造方法
公开(公告)号：US08673722B2
公开(公告)日：2014-03-18
申请号：US13255443
申请日：2011-03-23
申请人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
发明人： Ru Huang , Quanxin Yun , Xia An , Yujie Al , Xing Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/66545 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848 , H01L29/7849
摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.
摘要翻译：本发明公开了一种应变通道场效应晶体管及其制造方法。场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力。

4. 发明申请

US20130161757A1 CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof 有权
标题翻译：用于降低电荷共享效应的CMOS器件及其制造方法
公开(公告)号：US20130161757A1
公开(公告)日：2013-06-27
申请号：US13582034
申请日：2012-04-16
申请人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
发明人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/02203 , H01L21/02216 , H01L21/3063 , H01L21/823878 , H01L27/0921
摘要： The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.
摘要翻译：本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。附加隔离区的材料是多孔硅。由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料，因此在多孔硅的表面层上存在大量微孔和悬挂键。这些缺陷可能在多孔硅的禁带的中心形成缺陷状态，缺陷状态可能会捕获载体以引起增加的电阻。随着腐蚀电流密度的增加，孔隙率增加，多孔硅中的缺陷增加。本发明可以通过使用多孔硅捕集载体中的缺陷状态，浅沟槽隔离（STI）区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应，并且该工艺简单，从而可以大大提高集成电路的射电阻性能。

5. 发明申请

US20130119445A1 CMOS DEVICE FOR REDUCING RADIATION-INDUCED CHARGE COLLECTION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：用于减少辐射诱导电荷收集的CMOS器件及其制造方法
公开(公告)号：US20130119445A1
公开(公告)日：2013-05-16
申请号：US13509170
申请日：2011-11-30
申请人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
发明人： Ru Huang , Fei Tan , Xia An , Qianqian Huang , Dong Yang , Xing Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6653 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.
摘要翻译：用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。在CMOS器件中，重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。该区域具有与源极区域和漏极区域相反的掺杂类型，并且具有不小于源极区域和漏极区域的掺杂浓度。电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分，并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围，使得可以在电场的力作用下立即收集的电荷减少。

6. 发明授权

US09171593B2 Multi-granularity parallel storage system 有权
标题翻译：多粒度并行存储系统
公开(公告)号：US09171593B2
公开(公告)日：2015-10-27
申请号：US14117295
申请日：2011-12-31
申请人： Donglin Wang , Zijun Liu , Xiaojun Xue , Xing Zhang , Zhiwei Zhang , Shaolin Xie
发明人： Donglin Wang , Zijun Liu , Xiaojun Xue , Xing Zhang , Zhiwei Zhang , Shaolin Xie
IPC分类号： G06F12/02 , G11C7/10 , G06F3/06 , G06F12/06 , G11C11/406 , G11C21/00 , G06F9/38
CPC分类号： G11C7/1072 , G06F3/0601 , G06F9/3895 , G06F12/02 , G06F12/0607 , G11C11/40615 , G11C21/00
摘要： A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.
摘要翻译：包括多个存储器，移位发生器，地址增量查找单元，地址移位器，行地址生成器和多个地址加法器的多粒度并行存储系统。移位发生器被配置为产生移位值。地址增量查找单元被配置为生成地址移位器的输入数据。地址移位器被配置为通过Shift元素向右循环移位输入数据，然后输出移位的数据。行地址生成器被配置为生成行地址RowAddr，并将生成的行地址RowAddr输入到每个地址加法器的另一个输入端。每个地址加法器被配置为在两个输入端子处执行输入数据的非符号相加以获得其中一个存储器的读/写（R / W）地址，并将R / W地址输入到地址输入端的记忆。

7. 发明授权

US08865543B2 Ge-based NMOS device and method for fabricating the same 有权
标题翻译： Ge基NMOS器件及其制造方法
公开(公告)号：US08865543B2
公开(公告)日：2014-10-21
申请号：US13580971
申请日：2012-02-21
申请人： Ru Huang , Zhiqiang Li , Xia An , Yue Guo , Xing Zhang
发明人： Ru Huang , Zhiqiang Li , Xia An , Yue Guo , Xing Zhang
IPC分类号： H01L21/8242 , H01L29/78 , H01L29/66 , H01L29/51
CPC分类号： H01L29/66477 , H01L29/0895 , H01L29/16 , H01L29/41783 , H01L29/517 , H01L29/66643 , H01L29/78
摘要： The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
摘要翻译：本发明的实施例提供了一种基于Ge的NMOS器件结构及其制造方法。通过使用该方法，在源极/漏极区域和衬底之间沉积氧化锗（GeO 2）和金属氧化物的双电介质层。本发明不仅降低了金属/ Ge接触的电子肖特基势垒高度，而且提高了基于Ge的肖特基的电流切换比，从而提高了Ge基肖特基NMOS晶体管的性能。此外，制造工艺非常容易和完全兼容硅CMOS工艺。与传统的制造方法相比，本发明中的Ge基NMOS器件结构和制造方法可以容易且有效地改善Ge基肖特基NMOS晶体管的性能。

8. 发明申请

US20140117465A1 GE-BASED NMOS DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：基于GE的NMOS器件及其制造方法
公开(公告)号：US20140117465A1
公开(公告)日：2014-05-01
申请号：US13580971
申请日：2012-02-21
申请人： Ru Huang , Zhiqiang Li , Xia An , Yue Guo , Xing Zhang
发明人： Ru Huang , Zhiqiang Li , Xia An , Yue Guo , Xing Zhang
IPC分类号： H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66477 , H01L29/0895 , H01L29/16 , H01L29/41783 , H01L29/517 , H01L29/66643 , H01L29/78
摘要： The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
摘要翻译：本发明的实施例提供了一种基于Ge的NMOS器件结构及其制造方法。通过使用该方法，在源极/漏极区域和衬底之间沉积氧化锗（GeO 2）和金属氧化物的双电介质层。本发明不仅降低了金属/ Ge接触的电子肖特基势垒高度，而且提高了基于Ge的肖特基的电流切换比，从而提高了Ge基肖特基NMOS晶体管的性能。此外，制造工艺非常容易和完全兼容硅CMOS工艺。与传统的制造方法相比，本发明中的Ge基NMOS器件结构和制造方法可以容易且有效地改善Ge基肖特基NMOS晶体管的性能。

9. 发明授权

US08632691B2 Interface treatment method for germanium-based device 有权
标题翻译：锗基装置的界面处理方法
公开(公告)号：US08632691B2
公开(公告)日：2014-01-21
申请号：US13702562
申请日：2012-06-14
申请人： Ru Huang , Min Li , Xia An , Ming Li , Meng Lin , Xing Zhang
发明人： Ru Huang , Min Li , Xia An , Ming Li , Meng Lin , Xing Zhang
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , C25F3/00
CPC分类号： H01L21/02052 , H01L21/306
摘要： Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on the surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device.
摘要翻译：本文公开了一种锗系器件的接口处理方法，属于超大规模集成（ULSI）电路制造技术领域。在该方法中，通过使用质量百分比浓度为15％〜36％的浓盐酸溶液除去锗系基板表面上的天然氧化物层，并且通过使表面的悬空键进行钝化处理使用质量百分比浓度为5％〜10％的稀盐酸溶液，以在表面上形成稳定的钝化层。该方法为清洗和钝化后在锗基基板表面上沉积高K（高介电常数）栅极电介质提供了良好的基础，提高了栅极电介质和基板之间界面的质量，改善了电气锗系MOS器件的性能。

10. 发明申请

US20130103351A1 Method for Predicting Reliable Lifetime of SOI Mosfet Device 有权
标题翻译：用于预测SOI Mosfet器件可靠寿命的方法
公开(公告)号：US20130103351A1
公开(公告)日：2013-04-25
申请号：US13504433
申请日：2011-11-30
申请人： Ru Huang , Dong Yang , Xia An , Xing Zhang
发明人： Ru Huang , Dong Yang , Xia An , Xing Zhang
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/287
摘要： Disclosed herein is a method for predicting a reliable lifetime of a SOI MOSFET device. The method comprises: measuring a relationship of a gate resistance of the SOI MOSFET device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the SOI MOSFET device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the SOI MOSFET device under a bias. The embodiment of the invention prevents the self-heating effect from affecting the SOI MOSFET device in a practical logic circuit or in an AC analog circuit, which leads to a more precise prediction result.
摘要翻译：这里公开了一种用于预测SOI MOSFET器件的可靠寿命的方法。该方法包括：测量SOI MOSFET器件的栅极电阻与不同晶片温度下温度变化的关系; 在不同晶片温度下对SOI MOSFET器件进行寿命加速测试，以获得表示器件寿命作为应力时间的函数的退化关系，并在存在自热的情况下获得寿命参数退化为10％; 通过使用测量的自热温度和Arrhenius模型对器件的测量寿命进行自加热校正，以获得没有自热影响的寿命; 对由自加热引起的漏极电流的变化进行自热校正; 对热载体产生的冲击电离率进行自热校正; 并且在偏压下预测SOI MOSFET器件的寿命。本发明的实施例防止了自发热效应影响实际逻辑电路或AC模拟电路中的SOI MOSFET器件，这导致更精确的预测结果。

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