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    • 2. 发明授权
    • Ge-based NMOS device and method for fabricating the same
    • Ge基NMOS器件及其制造方法
    • US08865543B2
    • 2014-10-21
    • US13580971
    • 2012-02-21
    • Ru HuangZhiqiang LiXia AnYue GuoXing Zhang
    • Ru HuangZhiqiang LiXia AnYue GuoXing Zhang
    • H01L21/8242H01L29/78H01L29/66H01L29/51
    • H01L29/66477H01L29/0895H01L29/16H01L29/41783H01L29/517H01L29/66643H01L29/78
    • The embodiments of the present invention provide a Ge-based NMOS device structure and a method for fabricating the same. By using the method, double dielectric layers of germanium oxide (GeO2) and metal oxide are deposited between the source/drain region and the substrate. The present invention not only reduces the electron Schottky barrier height of metal/Ge contact, but also improves the current switching ratio of the Ge-based Schottky and therefore, it will improve the performance of the Ge-based Schottky NMOS transistor. In addition, the fabrication process is very easy and completely compatible with the silicon CMOS process. As compared with conventional fabrication method, the Ge-based NMOS device structure and the fabrication method in the present invention can easily and effectively improve the performance of the Ge-based Schottky NMOS transistor.
    • 本发明的实施例提供了一种基于Ge的NMOS器件结构及其制造方法。 通过使用该方法,在源极/漏极区域和衬底之间沉积氧化锗(GeO 2)和金属氧化物的双电介质层。 本发明不仅降低了金属/ Ge接触的电子肖特基势垒高度,而且提高了基于Ge的肖特基的电流切换比,从而提高了Ge基肖特基NMOS晶体管的性能。 此外,制造工艺非常容易和完全兼容硅CMOS工艺。 与传统的制造方法相比,本发明中的Ge基NMOS器件结构和制造方法可以容易且有效地改善Ge基肖特基NMOS晶体管的性能。
    • 4. 发明授权
    • Electrical connector
    • 电连接器
    • US08376785B2
    • 2013-02-19
    • US13179016
    • 2011-07-08
    • Doron LapidotZhiqiang LiHuibin Li
    • Doron LapidotZhiqiang LiHuibin Li
    • H01R24/00
    • H01R13/6461H01R24/60
    • An electrical connector having an insulative housing, a plurality of first terminals and a plurality of second terminals. The first terminals are disposed in the insulative housing. Each of the first terminals has a first contact portion, a first solder portion, and a first connection portion between the first contact portion and the first solder portion. The plurality of second terminals are also disposed in the insulative housing. Each of the second terminals has a second contact portion, a second solder portion, and a second connection portion between the second contact portion and the second solder portion. The first solder portions of the first terminals and the second solder portions of the second terminals are arranged in two rows in a lateral direction, respectively. The row of the first solder portions is separated from the row of the second solder portions by a predetermined distance in a longitudinal direction.
    • 一种具有绝缘壳体,多个第一端子和多个第二端子的电连接器。 第一端子设置在绝缘壳体中。 每个第一端子具有第一接触部分,第一焊接部分和第一接触部分与第一焊接部分之间的第一连接部分。 多个第二端子也设置在绝缘壳体中。 每个第二端子具有第二接触部分,第二焊接部分和第二接触部分和第二焊接部分之间的第二连接部分。 第一端子的第一焊接部分和第二端子的第二焊接部分分别沿横向布置成两行。 第一焊料部分的行与第二焊料部分的行在纵向方向上分开预定距离。
    • 10. 发明申请
    • GERMANIUM-BASED NMOS DEVICE AND METHOD FOR FABRICATING THE SAME
    • 基于锗的NMOS器件及其制造方法
    • US20130069126A1
    • 2013-03-21
    • US13519857
    • 2012-02-21
    • Ru HuangZhiqiang LiXia AnYue GuoXing Zhang
    • Ru HuangZhiqiang LiXia AnYue GuoXing Zhang
    • H01L29/78H01L21/283
    • H01L29/41783H01L29/0895H01L29/517H01L29/66643H01L29/78
    • An embodiment of the invention provides a germanium-based NMOS device and a method for fabricating the same, which relates to fabrication process technology of an ultra-large-scale-integrated (ULSI) circuit. The germanium-based NMOS device has two dielectric layer interposed between a metal source/drain and a substrate. The bottom dielectric layer includes a dielectric material having a high pinning coefficient S such as hafnium oxide, silicon nitride, hafnium silicon oxide or the like, and the top dielectric layer includes a dielectric material having a low conduction band offset ΔEC such as titanium oxide, gallium oxide, strontium titanium oxide or the like. According to the method, Fermi level pinning effect can be alleviated, electron barrier height can be lowered, and thus performance of the germanium-based Schottky NMOS device can be improved. Compared with a conventional single dielectric layer such as aluminum oxide (Al2O3), Schottky barrier height can be lowered while low source/drain resistances can be maintained, and thus performance of the device can be significantly improved.
    • 本发明的实施例提供了一种基于锗的NMOS器件及其制造方法,涉及超大规模集成(ULSI)电路的制造工艺技术。 锗基NMOS器件具有介于金属源极/漏极和衬底之间的两个介电层。 底部电介质层包括具有高钉扎系数S的介电材料,例如氧化铪,氮化硅,氧化铪等,并且顶部电介质层包括具有低导带偏移&Dgr; EC的介电材料,例如钛 氧化物,氧化镓,氧化钛锶等。 根据该方法,可以减轻费米能级钉扎效应,降低电子势垒高度,从而提高锗基肖特基NMOS器件的性能。 与常规的单一电介质层如氧化铝(Al2O3)相比,可以降低肖特基势垒高度,同时保持低的源极/漏极电阻,从而显着提高器件的性能。