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1. 发明授权

US07115530B2 Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权
标题翻译：使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低
公开(公告)号：US07115530B2
公开(公告)日：2006-10-03
申请号：US10726987
申请日：2003-12-03
申请人： Manuel A. Quevedo-Lopez , James J. Chambers , Luigi Colombo , Mark R. Visokay
发明人： Manuel A. Quevedo-Lopez , James J. Chambers , Luigi Colombo , Mark R. Visokay
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译：具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。

2. 发明授权

US07135361B2 Method for fabricating transistor gate structures and gate dielectrics thereof 有权
标题翻译：制造晶体管栅极结构及其栅极电介质的方法
公开(公告)号：US07135361B2
公开(公告)日：2006-11-14
申请号：US10734708
申请日：2003-12-11
申请人： Mark R. Visokay , Luigi Colombo , James J. Chambers , Antonio L. P. Rotondaro , Haowen Bu
发明人： Mark R. Visokay , Luigi Colombo , James J. Chambers , Antonio L. P. Rotondaro , Haowen Bu
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译：公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入栅电介质。可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。

3. 发明授权

US07098516B2 Refractory metal-based electrodes for work function setting in semiconductor devices 有权
$Refractory metal-based electrodes for work function setting in semiconductor devices$
标题翻译：用于半导体器件功能设置的耐火金属基电极
公开(公告)号：US07098516B2
公开(公告)日：2006-08-29
申请号：US10852523
申请日：2004-05-24
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译：本发明在一个实施例中提供一种栅极结构（100）。栅极结构包括栅极电介质（105）和栅极（110）。栅极电介质包括难熔金属并且位于半导体衬底（115）之上。半导体衬底具有导带和价带。栅极位于栅极电介质上方并且包括难熔金属。栅极具有与导带或价带对准的功函数。其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

4. 发明申请

US20100155860A1 TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER 审中-公开
标题翻译：使用物理蒸气沉积层和化学气相沉积层创建门电极的两步法
公开(公告)号：US20100155860A1
公开(公告)日：2010-06-24
申请号：US12344046
申请日：2008-12-24
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Majid Mansoori
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Majid Mansoori
IPC分类号： H01L29/43 , H01L21/283 , H01L21/336 , C23C14/34
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/66545
摘要： One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode.
摘要翻译：本发明的一个实施例涉及通过利用用于形成栅电极的两步沉积方法形成的半导体器件，而不会对下面的栅介质材料造成损害。在一个实施例中，使用不损坏栅极电介质材料（例如，物理气相沉积）的沉积，在栅极电介质材料的表面上形成第一层栅电极材料（第一栅电极层），从而导致损坏栅介电材料和栅电极材料之间的自由界面。然后使用提供增加的沉积控制（例如，良好的层均匀性，杂质控制等）的化学沉积方法将第二层栅电极材料（第二栅极电极层）形成在第一层栅电极材料层上。然后，第一和第二栅极电极层被选择性地图案化以累积地形成半导体器件的栅电极。

5. 发明授权

US07351626B2 Method for controlling defects in gate dielectrics 有权
标题翻译：控制栅极电介质缺陷的方法
公开(公告)号：US07351626B2
公开(公告)日：2008-04-01
申请号：US10739617
申请日：2003-12-18
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/02323 , H01L21/28185 , H01L21/28194 , H01L21/3143 , H01L21/31608 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/318 , H01L29/518 , H01L29/78
摘要： A method for improving high-κ gate dielectric film (104) properties. The high-κ film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.
摘要翻译：一种改善高卡门电介质膜（104）性能的方法。对高卡帕膜（104）进行两步退火处理。第一退火在具有低分压氧化剂的还原环境（106）中进行，以促进膜弛豫并增加副产物扩散和解吸附。第二次退火在具有低分压还原剂的氧化环境（108）中进行以除去缺陷和杂质。

6. 发明授权

US06809370B1 High-k gate dielectric with uniform nitrogen profile and methods for making the same 有权
标题翻译：具有均匀氮分布的高k栅极电介质及其制造方法
公开(公告)号：US06809370B1
公开(公告)日：2004-10-26
申请号：US10632230
申请日：2003-07-31
申请人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
发明人： Luigi Colombo , Manuel Quevedo-Lopez , James J. Chambers , Mark R. Visokay , Antonio L. P. Rotondaro
IPC分类号： H01L27108
CPC分类号： H01L29/518 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/6659 , H01L29/7833
摘要： High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.
摘要翻译：提供了高k晶体管栅极结构及其制造方法，其中在半导体衬底附近的栅极电介质界面区域设置有非常少的或不具有氮的，而本体高k电介质具有均匀的氮浓度。

7. 发明申请

US20120164820A1 SEMICONDUCTOR DEVICE FABRICATED USING A METAL MICROSTRUCTURE CONTROL PROCESS 有权
标题翻译：使用金属微结构控制过程制造的半导体器件
公开(公告)号：US20120164820A1
公开(公告)日：2012-06-28
申请号：US13404840
申请日：2012-02-24
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译：本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向进行氢退火。

8. 发明授权

US08124529B2 Semiconductor device fabricated using a metal microstructure control process 有权
标题翻译：使用金属微结构控制工艺制造的半导体器件
公开(公告)号：US08124529B2
公开(公告)日：2012-02-28
申请号：US11421671
申请日：2006-06-01
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/44
CPC分类号： H01L21/28079 , H01L21/02068 , H01L21/3003 , H01L21/321 , H01L21/823842
摘要： The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.
摘要翻译：本发明提供了一种制造半导体器件的方法，该方法包括将金属栅极层放置在栅极电介质层上，其中金属栅极层具有晶体取向，并通过对金属栅极层进行金属栅极层的重新取向来取向晶体取向进行氢退火。

9. 发明授权

US07528024B2 Dual work function metal gate integration in semiconductor devices 有权
标题翻译：双功能金属门集成在半导体器件中
公开(公告)号：US07528024B2
公开(公告)日：2009-05-05
申请号：US10890365
申请日：2004-07-13
申请人： Luigi Colombo , James J. Chambers , Mark R. Visokay
发明人： Luigi Colombo , James J. Chambers , Mark R. Visokay
IPC分类号： H01L21/28 , H01L21/338 , H01L21/44
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).
摘要翻译：本发明在一个实施例中提供了一种用于形成双功函数金属栅极半导体器件（100）的工艺。该方法包括提供其上具有栅极电介质层（110）的半导体衬底（105）和栅极电介质层上的金属层（205）。金属层的功函数与半导体衬底的导带或价带相匹配。该方法还包括在金属层的一部分（215）和金属层上的材料层（305）上形成导电阻挡层（210）。对金属层和材料层进行退火以形成金属合金层（405），从而将金属合金层的功函数与衬底的导带或价带中的另一个相匹配。本发明的其它实施例包括双功函数金属栅极半导体器件（900）和集成电路（1000）。

10. 发明申请

US20120231590A1 Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device 审中-公开
标题翻译：设置完全硅化半导体器件的功能的方法及相关器件
公开(公告)号：US20120231590A1
公开(公告)日：2012-09-13
申请号：US13474927
申请日：2012-05-18
申请人： Luigi Colombo , Mark R. Visokay , James J. Chambers
发明人： Luigi Colombo , Mark R. Visokay , James J. Chambers
IPC分类号： H01L21/28 , H01L21/8238
CPC分类号： H01L21/823835 , H01L21/28079 , H01L21/28097 , H01L21/28176 , H01L21/28518 , H01L21/76819 , H01L21/823842
摘要： A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.
摘要翻译：一种设置硅化半导体器件功能的方法及相关器件。示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物层层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 介电层界面。

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