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1. 发明授权

US07611939B2 Semiconductor device manufactured using a laminated stress layer 有权
标题翻译：使用层压应力层制造的半导体器件
公开(公告)号：US07611939B2
公开(公告)日：2009-11-03
申请号：US11745044
申请日：2007-05-07
申请人： Manoj Mehrotra , Antonio L. P. Rotondaro , Puneet Kohli
发明人： Manoj Mehrotra , Antonio L. P. Rotondaro , Puneet Kohli
IPC分类号： H01L21/8238
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76828 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.
摘要翻译：提出了形成半导体器件的方法。该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底之上形成层压应力层。层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

2. 发明申请

US20090179280A1 HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE 有权
标题翻译：具有As，P和C的高阈值NMOS源 - 漏极形成以减少损害
公开(公告)号：US20090179280A1
公开(公告)日：2009-07-16
申请号：US11972417
申请日：2008-01-10
申请人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
发明人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823418 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed
摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。碳植入通常用于减少NLDD中的磷扩散，但有助于门极二极管泄漏（GDL）。在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。还公开了在NSD中具有小于1.1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管

3. 发明申请

US20080277730A1 Semiconductor Device Manufactured Using a Laminated Stress Layer 有权
标题翻译：使用层压应力层制造的半导体器件
公开(公告)号：US20080277730A1
公开(公告)日：2008-11-13
申请号：US11745044
申请日：2007-05-07
申请人： Manoj Mehrotra , Antonio L.P Rotondaro , Puneet Kohli
发明人： Manoj Mehrotra , Antonio L.P Rotondaro , Puneet Kohli
IPC分类号： H01L21/44 , H01L29/76
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76828 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.
摘要翻译：提出了形成半导体器件的方法。该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底上形成层压应力层。层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

4. 发明申请

US20080076227A1 METHOD FOR FORMING A PRE-METAL DIELECTRIC LAYER USING AN ENERGY BEAM TREATMENT 审中-公开
标题翻译：使用能量束处理形成预金属介电层的方法
公开(公告)号：US20080076227A1
公开(公告)日：2008-03-27
申请号：US11533795
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/2686 , H01L21/76224 , H01L21/76825 , H01L29/6659 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes, among other steps, forming a gate structure over a substrate, the gate structure having source/drain regions proximate thereto and in, on or over the substrate, forming a pre-metal dielectric layer over the gate structure and source/drain regions, and subjecting the pre-metal dielectric layer to an energy beam treatment, the energy beam treatment configured to change a stress of the pre-metal dielectric layer, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法包括在衬底上形成栅极结构，栅极结构具有靠近其的源极/漏极区域，并且在衬底上，衬底上或上方，在栅极上形成预金属电介质层结构和源极/漏极区域，并且对金属前介电层进行能量束处理，所述能量束处理被配置为改变预金属介电层的应力，从而改变其下的衬底中的应力。

5. 发明授权

US07897496B2 Semiconductor doping with reduced gate edge diode leakage 有权
标题翻译：半导体掺杂减少了栅极边缘二极管泄漏
公开(公告)号：US07897496B2
公开(公告)日：2011-03-01
申请号：US11941129
申请日：2007-11-16
申请人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
发明人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/165 , H01L29/6659 , H01L29/7833
摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.
摘要翻译：公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中，漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

6. 发明授权

US07465635B2 Method for manufacturing a gate sidewall spacer using an energy beam treatment 有权
标题翻译：使用能量束处理制造栅极侧壁间隔物的方法
公开(公告)号：US07465635B2
公开(公告)日：2008-12-16
申请号：US11533798
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法可以包括在衬底上形成栅极结构，形成靠近栅极结构的侧壁的栅极侧壁间隔的至少一部分，以及使栅极侧壁间隔物的至少一部分能量束处理被配置为改变栅极侧壁间隔物的至少一部分的应力，从而改变其下的衬底中的应力。

7. 发明授权

US07846783B2 Use of poly resistor implant to dope poly gates 有权
标题翻译：使用多晶硅电阻植入来掺杂多晶硅栅极
公开(公告)号：US07846783B2
公开(公告)日：2010-12-07
申请号：US12265358
申请日：2008-11-05
申请人： Manoj Mehrotra , Puneet Kohli
发明人： Manoj Mehrotra , Puneet Kohli
IPC分类号： H01L21/335
CPC分类号： H01L27/0629
摘要： A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC.
摘要翻译：公开了一种制造IC的工艺，其中同时注入多晶硅电阻器和MOS晶体管的栅极区域。同时植入可用于减少IC制造顺序中的步骤。同时植入也可用于在IC中提供另一种具有增强性能的晶体管。可以与p型多晶硅电阻同时注入窄PMOS晶体管栅极，以增加导通状态驱动电流。厚栅极电介质上的PMOS晶体管栅极可以与p型多晶硅电阻同时注入，以减少栅极耗尽。 NMOS晶体管栅极可以与n型多晶硅电阻同时注入以减少栅极耗尽，并且可以与p型多晶硅电阻同时注入，以在IC中提供高阈值NMOS晶体管。

8. 发明申请

US20080146043A1 METHOD FOR MANUFACTURING AN ISOLATION STRUCTURE USING AN ENERGY BEAM TREATMENT 有权
标题翻译：使用能量束处理制造隔离结构的方法
公开(公告)号：US20080146043A1
公开(公告)日：2008-06-19
申请号：US11610758
申请日：2006-12-14
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/00
CPC分类号： H01L21/3105 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.
摘要翻译：本发明提供一种制造半导体器件的方法。用于制造半导体器件的方法尤其可以包括在衬底的开口内形成一层或多层材料，所述开口和所述一层或多层形成隔离结构的至少一部分，并使至少一层的能量束处理，所述能量束处理被配置为改变受其影响的一个或多个层的应力，从而改变衬底中的应力。

9. 发明授权

US07960238B2 Multiple indium implant methods and devices and integrated circuits therefrom 有权
标题翻译：多种铟注入方法和装置以及集成电路
公开(公告)号：US07960238B2
公开(公告)日：2011-06-14
申请号：US12344843
申请日：2008-12-29
申请人： Puneet Kohli , Manoj Mehrotra
发明人： Puneet Kohli , Manoj Mehrotra
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/26513 , H01L21/823412 , H01L29/1083 , H01L29/66507 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm−3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface. A method to form an IC including at least one NMOS transistor includes implanting a first In implant at a first energy and a second In implant at a second energy, wherein the first In implant together with the second In implant form an In region having a retrograde profile under at least a portion of the channel region, and wherein the second energy is at least 5 keV more than the first energy.
摘要翻译：集成电路（IC）包括至少一个NMOS晶体管，其中NMOS晶体管包括具有半导体表面的衬底，以及形成在栅极电介质上的包括栅电极的表面中或其上的栅堆叠，其中沟道区域位于在栅极电介质下方的半导体表面。源极和漏极区域在栅极堆叠的相对侧上。具有逆行轮廓的An In区域在通道区域的至少一部分的下方。逆行曲线包括（i）与栅极电介质的半导体表面界面处的表面In浓度小于5×10 16 cm -3，（ii）从栅极电介质下方的半导体表面至少20nm的峰In浓度，并且其中（iii）峰In浓度比半导体表面界面处的In浓度高至少两（2）个数量级。一种形成包括至少一个NMOS晶体管的IC的方法，包括以第二能量以第一能量和第二In的植入物注入第一InNo，其中第一In植入物与第二In植入物一起形成具有逆行的In区域在所述通道区域的至少一部分下形成，并且其中所述第二能量比所述第一能量多至少5keV。

10. 发明授权

US07524777B2 Method for manufacturing an isolation structure using an energy beam treatment 有权
标题翻译：使用能量束处理制造隔离结构的方法
公开(公告)号：US07524777B2
公开(公告)日：2009-04-28
申请号：US11610758
申请日：2006-12-14
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/00
CPC分类号： H01L21/3105 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L29/7846
摘要： The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.
摘要翻译：本发明提供一种制造半导体器件的方法。用于制造半导体器件的方法尤其可以包括在衬底的开口内形成一层或多层材料，所述开口和所述一层或多层形成隔离结构的至少一部分，并使至少一层的能量束处理，所述能量束处理被配置为改变受其影响的一个或多个层的应力，从而改变衬底中的应力。

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