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1. 发明授权

US07215138B1 Programmable lookup table with dual input and output terminals in shift register mode 有权
标题翻译：可编程查找表，带有移位寄存器模式的双输入和输出端子
公开(公告)号：US07215138B1
公开(公告)日：2007-05-08
申请号：US11152590
申请日：2005-06-14
申请人： Venu M. Kondapalli , Trevor J. Bauer , Manoj Chirania , Philip D. Costello , Steven P. Young
发明人： Venu M. Kondapalli , Trevor J. Bauer , Manoj Chirania , Philip D. Costello , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/1736 , H03K19/17728 , H03K19/1776
摘要： A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N−1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N−2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.
摘要翻译：用于集成电路（IC）的可编程查找表可选地在编程为用作移位寄存器逻辑时提供两个输入信号和两个输出信号到可编程IC的互连结构。根据一个实施例，集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT），其中N是整数。 LUT可以被配置为用作具有输入信号移位和耦合到互连结构的一个输出信号的（2 **（N-1））位移位寄存器，或者作为二（2 **（N- 2）） - 具有耦合到互连结构的输入信号中的两个移位和两个输出信号的位移位寄存器。在一些实施例中，移位寄存器的每个位包括LUT的两个存储单元，用作主锁存器的第一存储器单元和用作从锁存器的第二存储器单元。

2. 发明授权

US07265576B1 Programmable lookup table with dual input and output terminals in RAM mode 有权
标题翻译：可编程查找表，具有RAM模式下的双输入和输出端子
公开(公告)号：US07265576B1
公开(公告)日：2007-09-04
申请号：US11152736
申请日：2005-06-14
申请人： Venu M. Kondapalli , Trevor J. Bauer , Manoj Chirania , Philip D. Costello , Steven P. Young
发明人： Venu M. Kondapalli , Trevor J. Bauer , Manoj Chirania , Philip D. Costello , Steven P. Young
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728
摘要： A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N−1))×2 RAM) having fewer than N (e.g., N−1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N−1)-bit shift register or two 2**(N−2)-bit shift registers.
摘要翻译：当编程为用作随机存取存储器（RAM）时，可编程查找表可选地向可编程集成电路的互连结构提供两个输入信号和两个输出信号。集成电路包括互连结构和具有耦合到互连结构的输入和输出端子的N输入查找表（LUT）。 LUT可以被配置为用作具有耦合到互连结构的N个输入地址信号和耦合到互连结构的一个输出信号的单位宽RAM（例如，（2 ** N）x1 RAM），或者作为具有小于N（例如，N-1）个输入地址信号的耦合到互连结构的多位宽RAM（例如，（2 **（N-1））×2 RAM）以及耦合到互连结构的至少两个输出信号互连结构。可选地，LUT也可以被配置为移位寄存器逻辑，例如2 **（N-1）位移位寄存器或两个2 **（N-2）位移位寄存器。

3. 发明授权

US07518394B1 Process monitor vehicle 有权
标题翻译：过程监控车
公开(公告)号：US07518394B1
公开(公告)日：2009-04-14
申请号：US11703862
申请日：2007-02-07
申请人： Manoj Chirania , Philip D. Costello
发明人： Manoj Chirania , Philip D. Costello
IPC分类号： H03K19/00
CPC分类号： H03K19/1776 , H03K19/17764
摘要： A method and apparatus is provided for the implementation of a process monitor vehicle (PMV) for memory cells. The memory cell PMV is useful in characterizing drive strength of the N-type and P-type field effect transistors (FETs) that are used to implement the memory cell. The memory cell PMV may be used, for example, to measure the amount of margin available for memory cell flips and how process variation affects the memory cell write margin. The memory cell PMV is implemented as a plurality of shift register bits interconnected as a ring oscillator, where each shift register bit is comprised of a memory cell. By adjusting the drive current for each memory cell and measuring the resultant change in oscillation frequency of the ring oscillator, information may be obtained concerning process variation and its effect on memory cell performance.
摘要翻译：提供了一种用于实现用于存储器单元的过程监视器车辆（PMV）的方法和装置。存储单元PMV可用于表征用于实现存储单元的N型和P型场效应晶体管（FET）的驱动强度。存储单元PMV可以用于例如测量可用于存储器单元翻转的余量以及处理变化如何影响存储器单元写入余量。存储单元PMV被实现为作为环形振荡器互连的多个移位寄存器位，其中每个移位寄存器位由存储单元组成。通过调整每个存储单元的驱动电流并测量环形振荡器的振荡频率的变化，可以获得关于过程变化及其对存储单元性能的影响的信息。

4. 发明授权

US07653891B1 Method of reducing power of a circuit 有权
标题翻译：降低电路功率的方法
公开(公告)号：US07653891B1
公开(公告)日：2010-01-26
申请号：US11710096
申请日：2007-02-23
申请人： Jason H. Anderson , Manoj Chirania , Subodh Gupta , Philip D. Costello
发明人： Jason H. Anderson , Manoj Chirania , Subodh Gupta , Philip D. Costello
IPC分类号： H03K17/693
CPC分类号： H03K19/17784 , H03K17/005 , H03K17/16 , H03K19/00346 , H03K19/1731
摘要： A method of reducing power of a circuit is described. The method includes determining at least one unused selection input associated with stages of a multiplexer tree; pulling the at least one unused selection input to a constant value; and assigning predetermined values to unused data inputs of the multiplexer tree associated with the at least one unused selection input.
摘要翻译：描述了一种降低电路功率的方法。该方法包括确定与复用器树的阶段相关联的至少一个未使用的选择输入; 将至少一个未使用的选择输入拉至恒定值; 以及将预定值分配给与所述至少一个未使用的选择输入相关联的多路复用器树的未使用的数据输入。

5. 发明授权

US07600204B1 Method for simulation of negative bias and temperature instability 有权
标题翻译：模拟负偏压和温度不稳定的方法
公开(公告)号：US07600204B1
公开(公告)日：2009-10-06
申请号：US11706744
申请日：2007-02-14
申请人： Manoj Chirania , Philip D. Costello , Robert I-Che Fu
发明人： Manoj Chirania , Philip D. Costello , Robert I-Che Fu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An apparatus and method to accurately simulate negative bias and temperature instability (NBTI) and its effect. According to a first simulation method, a simulation netlist is automatically scanned for any P-type devices that are in a conductive state after application of an initial condition. Each conductive P-type device is automatically replaced with an NBTI device model and a first simulation cycle is executed. After the first cycle, each conductive P-type device is again replaced with an NBTI model and a second simulation cycle is executed. In a second simulation method, only those P-type devices transitioning from a non-conductive state to a conductive state are automatically replaced with an NBTI model prior to each half cycle of the second simulation method. The first simulation method provides robustness, while the second simulation method provides worst case verification in less time as compared to the first simulation method.
摘要翻译：准确模拟负偏压和温度不稳定性（NBTI）及其影响的装置和方法。根据第一模拟方法，对于在施加初始条件之后处于导通状态的任何P型装置，自动扫描模拟网表。每个导电P型器件都会自动替换为NBTI器件型号，并执行第一个仿真周期。在第一周期之后，每个导电P型装置再次被替换为NBTI模型，并且执行第二模拟循环。在第二仿真方法中，在第二仿真方法的每个半周期之前，只有从非导通状态转换到导通状态的P型器件将自动地被NBTI模型替代。第一种模拟方法提供了鲁棒性，而第二种模拟方法与第一种模拟方法相比，在较短的时间内提供了最差的验证。

6. 发明授权

US07256612B1 Programmable logic block providing carry chain with programmable initialization values 有权
标题翻译：可编程逻辑块提供具有可编程初始化值的进位链
公开(公告)号：US07256612B1
公开(公告)日：2007-08-14
申请号：US11151796
申请日：2005-06-14
申请人： Steven P. Young , Tien Pham , Philip D. Costello
发明人： Steven P. Young , Tien Pham , Philip D. Costello
IPC分类号： H03K19/173 , H03K19/177 , G06F7/38 , H01L25/00
CPC分类号： H03K19/17772 , G06F7/505 , G06F7/53 , H03K19/17728 , H03K19/17736
摘要： A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e.g., power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.
摘要翻译：一个可编程逻辑块为进位逻辑块提供可编程的初始化值，而不需要消耗用户的逻辑资源。示例性可编程逻辑块包括耦合在一起以形成可编程逻辑块的进位链的两个或多个进位多路复用器。进位初始化电路具有耦合到进位链中的第一进位多路复用器的数据输入端的输出端。携带初始化电路由可编程逻辑块的配置存储器单元控制，以选择进位信号，功率高信号，接地信号和（可选地）来自逻辑块的互连结构的信号之一。因此，可以向进位链提供初始化值（例如，功率高或接地），而不消耗逻辑块内的其他可编程资源。

7. 发明授权

US07283409B1 Data monitoring for single event upset in a programmable logic device 有权
标题翻译：可编程逻辑器件中单事件不正常的数据监控
公开(公告)号：US07283409B1
公开(公告)日：2007-10-16
申请号：US11503824
申请日：2006-08-14
申请人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
发明人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/1776
摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.
摘要翻译：描述用于错误检测的数据监视的方法和装置。可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。辅助地址线耦合到与功能发生器相关联的存储器单元组。掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

8. 发明授权

US07075333B1 Programmable circuit optionally configurable as a lookup table or a wide multiplexer 有权
标题翻译：可编程电路可选地配置为查找表或宽多路复用器
公开(公告)号：US07075333B1
公开(公告)日：2006-07-11
申请号：US10925259
申请日：2004-08-24
申请人： Kamal Chaudhary , Philip D. Costello , Venu M. Kondapalli
发明人： Kamal Chaudhary , Philip D. Costello , Venu M. Kondapalli
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00 , G06F7/38
CPC分类号： H03K19/1737 , H03K19/17728
摘要： Circuits that can be optionally programmed to function as lookup tables (LUTs) or wide multiplexers, and integrated circuits including these programmable circuits. A function select multiplexer is included between each memory cell and the corresponding data input terminal of a first multiplexer. Each function select multiplexer has a first data input terminal coupled to the corresponding memory cell, a second data input terminal coupled to an external input terminal, and a select terminal controlled by a value stored in a function select memory cell. When a first value is stored in the function select memory cell, the programmable circuit functions in the same fashion as a known LUT. When a second value is stored in the function select memory cell, the programmable circuit functions as a wide multiplexer, with the data input values being provided by the external input terminals.
摘要翻译：可选地编程为用作查找表（LUT）或多路复用器的电路，以及包括这些可编程电路的集成电路。每个存储单元和第一多路复用器的对应的数据输入端之间包括功能选择多路复用器。每个功能选择多路复用器具有耦合到对应的存储器单元的第一数据输入端子，耦合到外部输入端子的第二数据输入端子和由存储在功能选择存储器单元中的值控制的选择端子。当第一值存储在功能选择存储单元中时，可编程电路以与已知LUT相同的方式起作用。当第二个值存储在功能选择存储单元中时，可编程电路用作宽多路复用器，数据输入值由外部输入端提供。

9. 发明授权

US07109783B1 Method and apparatus for voltage regulation within an integrated circuit 有权
标题翻译：集成电路内电压调节的方法和装置
公开(公告)号：US07109783B1
公开(公告)日：2006-09-19
申请号：US10847966
申请日：2004-05-18
申请人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
发明人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.
摘要翻译：描述了用于调整集成电路内的电压的方法和装置。例如，电压调节器接收第一参考电压并产生调节电压。比较器包括用于接收第二参考电压的第一输入端和用于接收调节电压的第二输入端。比较器包括偏移电压。比较器产生指示第二参考电压和调节电压之间的差是否大于预定偏移电压的控制信号。钳位电路响应于控制信号将调节电压钳位到第二参考电压。在另一示例中，钳位电路被去除，并且多路复用器选择要耦合到电压调节器的第一参考电压或第二参考电压。通过比较第一参考电压和第二参考电压的比较器的输出来控制多路复用器。

10. 发明授权

US5936424A High speed bus with tree structure for selecting bus driver 失效
标题翻译：具有树型结构的高速总线，用于选择公共汽车司机
公开(公告)号：US5936424A
公开(公告)日：1999-08-10
申请号：US950380
申请日：1997-10-14
申请人： Steven P. Young , Kamal Chaudhary , Shekhar Bapat , Sridhar Krishnamurthy , Philip D. Costello
发明人： Steven P. Young , Kamal Chaudhary , Shekhar Bapat , Sridhar Krishnamurthy , Philip D. Costello
IPC分类号： H03K19/0175 , H03K19/173 , H03K19/0185 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/017581
摘要： According to the invention, a structure is provided for driving a bus line that is both fast and small. Instead of a plurality of tristate buffers, one for each input signal, a plurality of multiplexers or gates is connected into a tree structure. The tristate enable line of the tristate buffer becomes the control line for enabling the tree structure to place its own input signal onto the bus instead of propagating the signal already on the bus. A buffer element then allows the resulting signal to be tapped from the bus. One embodiment of the invention includes lookahead logic similar to a lookahead carry chain. This allows large numbers of input lines to be connected to a bus line while retaining high speed. The symmetrical delay of a tree structure minimizes the greatest delay and thus increases predicted speed.
摘要翻译：根据本发明，提供一种用于驱动快速且小的总线的结构。代替多个三态缓冲器，每个输入信号一个，多个多路复用器或门连接到树结构中。三态缓冲器的三态使能线路成为控制线，用于使树结构能够将其自己的输入信号放置在总线上，而不是传播已经在总线上的信号。然后，缓冲元件允许从总线中抽出所得到的信号。本发明的一个实施例包括类似于前瞻携带链的前瞻逻辑。这允许大量输入线连接到总线，同时保持高速。树结构的对称延迟使最大延迟最小化，从而增加预测速度。

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