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1. 发明授权

US07283409B1 Data monitoring for single event upset in a programmable logic device 有权
标题翻译：可编程逻辑器件中单事件不正常的数据监控
公开(公告)号：US07283409B1
公开(公告)日：2007-10-16
申请号：US11503824
申请日：2006-08-14
申请人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
发明人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/1776
摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.
摘要翻译：描述用于错误检测的数据监视的方法和装置。可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。辅助地址线耦合到与功能发生器相关联的存储器单元组。掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

2. 发明授权

US07109746B1 Data monitoring for single event upset in a programmable logic device 有权
标题翻译：可编程逻辑器件中单事件不正常的数据监控
公开(公告)号：US07109746B1
公开(公告)日：2006-09-19
申请号：US10806697
申请日：2004-03-22
申请人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
发明人： Martin L. Voogel , David P. Schultz , Vasisht M. Vadi , Philip D. Costello , Venu M. Kondapalli
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/1776
摘要： Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.
摘要翻译：描述用于错误检测的数据监视的方法和装置。可编程逻辑器件包括具有功能发生器的可配置逻辑块，其中每一个可配置用于至少两个可编程模式功能。功能发生器耦合到存储器单元阵列，用于存储用于配置功能发生器的配置位。主地址线耦合到跨越两个或更多个函数发生器的每个存储器单元。辅助地址线耦合到与功能发生器相关联的存储器单元组。掩模电路被配置为部分地响应于程序模式功能选择性地将主地址线的信号传送到辅助地址线的一个段或地址。

3. 发明授权

US07109783B1 Method and apparatus for voltage regulation within an integrated circuit 有权
标题翻译：集成电路内电压调节的方法和装置
公开(公告)号：US07109783B1
公开(公告)日：2006-09-19
申请号：US10847966
申请日：2004-05-18
申请人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
发明人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.
摘要翻译：描述了用于调整集成电路内的电压的方法和装置。例如，电压调节器接收第一参考电压并产生调节电压。比较器包括用于接收第二参考电压的第一输入端和用于接收调节电压的第二输入端。比较器包括偏移电压。比较器产生指示第二参考电压和调节电压之间的差是否大于预定偏移电压的控制信号。钳位电路响应于控制信号将调节电压钳位到第二参考电压。在另一示例中，钳位电路被去除，并且多路复用器选择要耦合到电压调节器的第一参考电压或第二参考电压。通过比较第一参考电压和第二参考电压的比较器的输出来控制多路复用器。

4. 发明授权

US06753722B1 Method and apparatus for voltage regulation within an integrated circuit 有权
标题翻译：集成电路内电压调节的方法和装置
公开(公告)号：US06753722B1
公开(公告)日：2004-06-22
申请号：US10354560
申请日：2003-01-30
申请人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
发明人： Venu M. Kondapalli , Martin L. Voogel , Philip D. Costello
IPC分类号： G05F110
CPC分类号： G05F1/56
摘要： Method and apparatus for regulating voltage within an integrated circuit is described. For example, a voltage regulator receives a first reference voltage and produces a regulated voltage. A comparator includes a first input for receiving a second reference voltage and a second input for receiving the regulated voltage. The comparator includes an offset voltage. The comparator produces a control signal indicative of whether the difference between the second reference voltage and the regulated voltage is greater than a predetermined offset voltage. A clamp circuit clamps the regulated voltage to the second reference voltage in response to the control signal. In another example, the clamp circuit is removed and a multiplexer selects either a first reference voltage or a second reference voltage to be coupled to a voltage regulator. The multiplexer is controlled via output of a comparator that compares the first reference voltage and the second reference voltage.
摘要翻译：描述了用于调整集成电路内的电压的方法和装置。例如，电压调节器接收第一参考电压并产生调节电压。比较器包括用于接收第二参考电压的第一输入端和用于接收调节电压的第二输入端。比较器包括偏移电压。比较器产生指示第二参考电压和调节电压之间的差是否大于预定偏移电压的控制信号。钳位电路响应于控制信号将调节电压钳位到第二参考电压。在另一示例中，钳位电路被去除，并且多路复用器选择要耦合到电压调节器的第一参考电压或第二参考电压。通过比较第一参考电压和第二参考电压的比较器的输出来控制多路复用器。

5. 发明授权

US06768338B1 PLD lookup table including transistors of more than one oxide thickness 有权
标题翻译： PLD查找表包括多于一个氧化物厚度的晶体管
公开(公告)号：US06768338B1
公开(公告)日：2004-07-27
申请号：US10354587
申请日：2003-01-30
申请人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F738
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.
摘要翻译：可用于例如实现可编程逻辑器件（PLD）的查找表的结构。该结构包括配置存储单元，传输晶体管和缓冲器。传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。在第一工作电压下提供数据输入信号。一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。

6. 发明授权

US07119570B1 Method of measuring performance of a semiconductor device and circuit for the same 有权
标题翻译：测量半导体器件性能的方法及其电路
公开(公告)号：US07119570B1
公开(公告)日：2006-10-10
申请号：US10836850
申请日：2004-04-30
申请人： Manoj Chirania , Venu M. Kondapalli , Martin L. Voogel , Philip Costello
发明人： Manoj Chirania , Venu M. Kondapalli , Martin L. Voogel , Philip Costello
IPC分类号： G01R31/26
CPC分类号： G01R31/31708 , G01R31/31725
摘要： A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.
摘要翻译：用于测试半导体器件上升延迟/下降延迟性能的测试电路可以包括锁存器，用于响应于时钟信号在其输入端锁存数据。锁存器可以输出与被锁存的数据相关的输出信号。作为时钟信号，缓冲链可以被配置为将由锁存器产生的信号从锁存器输出串行传播回到时钟输入。锁存器的复位/置位输入可被配置为从缓冲器链的中间节点接收复位/置位信号。

7. 发明授权

US06949951B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06949951B1
公开(公告)日：2005-09-27
申请号：US10869777
申请日：2004-06-15
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F7/38 , H03K17/00 , H03K17/693 , H03K19/177
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

8. 发明授权

US07053654B1 PLD lookup table including transistors of more than one oxide thickness 有权
标题翻译： PLD查找表包括多于一个氧化物厚度的晶体管
公开(公告)号：US07053654B1
公开(公告)日：2006-05-30
申请号：US10869139
申请日：2004-06-15
申请人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F7/38
CPC分类号： H03K19/1778 , H03K19/1737 , H03K19/17728
摘要： A structure that can be used, for example, to implement a lookup table for a programmable logic device (PLD). The structure includes configuration memory cells, pass transistors, and a buffer. The pass transistors pass the output of a selected configuration memory cell to the buffer, and are controlled by data input signals of the structure. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The memory cells and buffer include transistors having a second oxide thickness thinner than the first oxide thickness, and operate at a second operating voltage lower than the first operating voltage. The data input signals are provided at the first operating voltage. Some embodiments include data generating circuits that include transistors having the first oxide thickness. Gate lengths can also vary between the memory cell transistors, pass transistors, buffer transistors, and data generating circuits.
摘要翻译：可用于例如实现可编程逻辑器件（PLD）的查找表的结构。该结构包括配置存储单元，传输晶体管和缓冲器。传输晶体管将所选配置存储单元的输出传递到缓冲器，并由结构的数据输入信号控制。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。存储单元和缓冲器包括具有比第一氧化物厚度薄的第二氧化物厚度的晶体管，并且在低于第一工作电压的第二工作电压下工作。在第一工作电压下提供数据输入信号。一些实施例包括包括具有第一氧化物厚度的晶体管的数据产生电路。栅极长度也可以在存储单元晶体管，传输晶体管，缓冲晶体管和数据产生电路之间变化。

9. 发明授权

US06768335B1 Integrated circuit multiplexer including transistors of more than one oxide thickness 有权
标题翻译：集成电路多路复用器包括多于一个氧化物厚度的晶体管
公开(公告)号：US06768335B1
公开(公告)日：2004-07-27
申请号：US10354520
申请日：2003-01-30
申请人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
发明人： Steven P. Young , Michael J. Hart , Venu M. Kondapalli , Martin L. Voogel
IPC分类号： G06F738
CPC分类号： H03K17/005 , H03K17/693 , H03K19/17736 , H03K19/1778
摘要： A multiplexer that can be used, for example, in a programmable logic device (PLD). The multiplexer includes a plurality of pass transistors passing a selected one of several input values to an internal node, which drives a buffer that provides the multiplexer output signal. The pass transistors can be controlled, for example, by values stored in memory cells of a PLD. The pass transistors have a first oxide thickness and are controlled by a value having a first operating voltage. The buffer includes transistors having a second and thinner oxide thickness, and is operated at a second and lower operating voltage. Where memory cells are used to control the pass transistors, the memory cells include transistors having the first oxide thickness and operate at the first operating voltage. Some embodiments also include transistors of varying gate length for each of the pass transistors, buffer transistors, and memory cell transistors.
摘要翻译：可以用于例如可编程逻辑器件（PLD）中的多路复用器。多路复用器包括将多个输入值中选择的一个输入值传送到内部节点的多个传输晶体管，驱动提供多路复用器输出信号的缓冲器。可以例如通过存储在PLD的存储器单元中的值来控制传输晶体管。传输晶体管具有第一氧化物厚度并且由具有第一工作电压的值控制。缓冲器包括具有第二和较薄氧化物厚度的晶体管，并且在第二和较低工作电压下操作。在使用存储器单元来控制传输晶体管的情况下，存储单元包括具有第一氧化物厚度并在第一工作电压下工作的晶体管。一些实施例还包括用于每个传输晶体管，缓冲晶体管和存储单元晶体管的栅极长度变化的晶体管。

10. 发明授权

US06822894B1 Single event upset in SRAM cells in FPGAs with leaky gate transistors 有权
标题翻译：具有泄漏栅极晶体管的FPGA中的单元事件不正常
公开(公告)号：US06822894B1
公开(公告)日：2004-11-23
申请号：US10396883
申请日：2003-03-25
申请人： Philip D. Costello , Martin L. Voogel
发明人： Philip D. Costello , Martin L. Voogel
IPC分类号： G11C1100
CPC分类号： G11C11/4125
摘要： A memory device having single event upset (SEU) resistant circuitry includes a first inverter having an input and an output, a second inverter having an input and an output, a first transistor having a gate coupled to the input of the first inverter and having source and drain regions coupled to the output of the second inverter, and a second transistor having a gate coupled to the input of the second inverter and having source and drain regions coupled to the output of the first inverter.
摘要翻译：具有单事件镦粗（SEU）电阻电路的存储器件包括具有输入和输出的第一反相器，具有输入和输出的第二反相器，具有耦合到第一反相器的输入的栅极的第一晶体管，以及耦合到所述第二反相器的输出的漏极区域，以及第二晶体管，其栅极耦合到所述第二反相器的输入并且具有耦合到所述第一反相器的输出的源极和漏极区域。

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