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    • 6. 发明授权
    • Semiconductor device having multilayer wiring structure
    • 具有多层布线结构的半导体装置
    • US07719117B2
    • 2010-05-18
    • US11828727
    • 2007-07-26
    • Katsuhiro IshidaHiroshi SugiuraMakoto HasegawaKatsuya Ito
    • Katsuhiro IshidaHiroshi SugiuraMakoto HasegawaKatsuya Ito
    • H01L23/48
    • H01L23/5226H01L21/76838H01L23/53223H01L23/5329H01L2924/0002H01L2924/00
    • A semiconductor device includes a semiconductor substrate, a lower wiring layer formed on the semiconductor substrate, a first interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.
    • 半导体器件包括半导体衬底,形成在半导体衬底上的下部布线层,形成在下部布线层上并包括第一上表面和第二上表面的第一层间绝缘膜,第一上表面高于第二上表面 相对于半导体基板的表面的上表面,形成在层间绝缘膜中并包括与下布线层接触的第一底面的接触塞,与第二上表面齐平的第三上表面和与第二上表面齐平的第四上表面 所述第一上表面,形成在所述第一和第三上表面上并包括第一侧表面和与所述第一侧表面相对的第二侧表面的上布线层,以及形成在所述第二和第四上表面上的第二层间绝缘膜。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE HAVING MULTILAYER WIRING STRUCTURE
    • 具有多层布线结构的半导体器件
    • US20080036089A1
    • 2008-02-14
    • US11828727
    • 2007-07-26
    • Katsuhiro ISHIDAHiroshi SugiuraMakoto HasegawaKatsuya Ito
    • Katsuhiro ISHIDAHiroshi SugiuraMakoto HasegawaKatsuya Ito
    • H01L23/52
    • H01L23/5226H01L21/76838H01L23/53223H01L23/5329H01L2924/0002H01L2924/00
    • A semiconductor device includes a semiconductor substrate, and an interlayer wiring structure further including a lower wiring layer formed on the semiconductor substrate, a first interlayer an interlayer wiring layer including an interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces. a plurality of contact plugs each formed so as to extend through the interlayer insulating film to be brought into electrical contact with the lower wiring layer, an upper wiring layer patterned so as to be in electrical contact with upper faces of the contact plugs, and a recessed portion formed by recessing the interlayer insulating film and the contact plugs exposed in the interlayer wiring layer with respect to at least a portion with a short distance between wirings so as to correspond to a shape of the upper wiring layer.
    • 半导体器件包括半导体衬底和还包括形成在半导体衬底上的下布线层的层间布线结构,第一层间夹层,形成在下布线层上并包括第一上表面的层间绝缘膜, 第二上表面,第一上表面相对于半导体衬底的表面高于第二上表面;形成在层间绝缘膜中并包括与下布线层接触的第一底表面的接触塞,第三上表面 与第二上表面齐平,第四上表面与第一上表面齐平,上布线层形成在第一和第三上表面上,并且包括第一侧表面和与第一侧表面相对的第二侧表面,以及 形成在第二和第四上表面上的第二层间绝缘膜。 多个接触插塞各自形成为延伸穿过层间绝缘膜以与下布线层电接触,图案化以与触头的上表面电接触的上布线层,以及 相对于布线之间的短距离的至少一部分,使层间绝缘膜和暴露在层间布线层中的接触插塞凹陷而形成的凹部,以对应于上布线层的形状。