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    • 5. 发明授权
    • Shift register
    • 移位寄存器
    • US08457272B2
    • 2013-06-04
    • US12734218
    • 2008-08-26
    • Makoto YokoyamaShige FurutaYuhichiroh MurakamiYasushi Sasaki
    • Makoto YokoyamaShige FurutaYuhichiroh MurakamiYasushi Sasaki
    • G11C19/00
    • G11C19/184G09G3/3677G09G3/3688G09G2310/0286G09G2330/06G09G2330/08G11C19/28
    • At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
    • 本发明的至少一个实施例是多个单元电路以多级连接,当单元电路同时导通以输出高电平输出信号时,进行正常操作。 当移位寄存器发生故障时,使得由前一级和后级单元电路提供的输出信号同时设置为高电平,故障恢复电路并包括在单元电路中,在至少一个实施例中检测故障。 故障恢复电路向节点提供高电压,从而强制拉下输出信号。 此外,故障恢复电路强制地对另一个节点进行放电,从而释放在电容中累积的电荷。 结果,故障中的移位寄存器可以立即恢复正常运行。 本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。
    • 7. 发明授权
    • Pulse output circuit, and display device, drive circuit, display device, and pulse output method using same circuit
    • 脉冲输出电路,显示装置驱动电路,显示装置和使用同一电路的脉冲输出方式
    • US08330745B2
    • 2012-12-11
    • US12312216
    • 2007-11-19
    • Makoto YokoyamaYuhichiroh Murakami
    • Makoto YokoyamaYuhichiroh Murakami
    • G06F3/038G11C7/00
    • G09G3/3688G09G2310/0286G09G2310/0297G09G2310/08G11C19/00G11C19/28
    • In one embodiment of the present invention, a source driver includes a shift register including latch stages each including a level shifter that level-shifts clock signals so that the signals are fed into a set-reset flip-flop as inverted set input signals. Outputs from the set-reset flip-flop are delayed by a hazard preventing circuit and then fed into a level shifter in the next latch stage as enable signals. A delay trimming circuit causes a NAND circuit to perform a NAND operation with respect to outputs obtained by a delay of the outputs by a delay circuit and outputs from the level shifter in the next latch stage, so that a sampling pulse is derived. This allows for provision of a pulse output circuit capable of further trimming delay in output pulses and of securing a sufficient interval between the output pulses.
    • 在本发明的一个实施例中,源极驱动器包括一个移位寄存器,它包括锁存级,每个锁存级包括电平移位器,电平移位器使电平移位时钟信号,使得信号作为反相设置的输入信号被馈送到设置复位触发器。 来自置位触发器的输出由危险防止电路延迟,然后在下一个锁存级中馈送到电平移位器作为使能信号。 延迟微调电路使得NAND电路相对于由延迟电路的输出的延迟获得的输出和在下一个锁存级中的电平移位器的输出执行NAND操作,从而导出采样脉冲。 这允许提供能够进一步调整输出脉冲延迟并确保输出脉冲之间足够间隔的脉冲输出电路。