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1. 发明授权

US5373178A MOSFET with sidewall spacer on gate section 失效
标题翻译：栅极侧壁间隔MOSFET
公开(公告)号：US5373178A
公开(公告)日：1994-12-13
申请号：US095540
申请日：1993-07-26
申请人： Makoto Motoyoshi , Eita Kinoshita
发明人： Makoto Motoyoshi , Eita Kinoshita
IPC分类号： H01L27/11 , H01L21/336 , H01L21/768 , H01L21/8238 , H01L21/8244 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/76801 , H01L21/823864 , H01L21/823871 , H01L29/7833 , Y10S257/90
摘要： After forming a low concentration impurity layer by ion implanting an impurity into a semiconductor substrate 1 by using a gate electrode 7 on the semiconductor substrate 1 as a mask, side walls composed of films having a large etching resistivity with respect to an interlayer dielectric film 13 are formed on side surfaces of the gate electrode 7 and a gate oxide film 6 located beneath the gate electrode 7. Subsequently, the interlayer dielectric film 13 is formed over the whole surface, and a contact hole 18 having a part of side walls constituted by the first-mentioned side walls 8 and a field oxide film 2 is formed. A high concentration impurity layer is formed by implanting an impurity through the contact hole 18.
摘要翻译：通过使用半导体衬底1上的栅电极7作为掩模将杂质离子注入半导体衬底1中形成低浓度杂质层之后，由相对于层间绝缘膜13具有大的蚀刻电阻率的膜构成的侧壁形成在栅电极7的侧面和位于栅电极7下方的栅极氧化膜6.接着，在整个表面上形成层间电介质膜13，并且具有由侧壁构成的侧壁的一部分的接触孔18 首先形成侧壁8和场氧化膜2。通过将杂质注入接触孔18而形成高浓度杂质层。

2. 发明授权

US07362607B2 Solid-state memory device and method for arrangement of solid-state memory cells 有权
标题翻译：固态存储器件和固态存储器单元的布置方法
公开(公告)号：US07362607B2
公开(公告)日：2008-04-22
申请号：US11108699
申请日：2005-04-19
申请人： Makoto Motoyoshi
发明人： Makoto Motoyoshi
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , B82Y10/00 , G11C5/025 , G11C11/15 , G11C11/16
摘要： A high-capacity magnetic memory device in which the magnetic field for writing is nearly uniform for all memory elements. It is realized by reducing the deformation of resist pattern which occurs in photolithography when mask patterns are close to each other. The magnetic memory device is an MRAM composed of a large number of memory cells, each including one TMR element, one transistor for reading (selection), and reading plugs that connect the TMR element to the transistor for reading (selection). These memory cells are arranged such that the TMR elements are in a pattern of translational symmetry. For writing, memory cells are connected by the bit lines and the writing word lines which intersect orthogonally. The long axis of the TMR element is oriented aslant 45° with respect to these lines, so that the TMR elements are capable of toggle-mode writing.
摘要翻译：一种大容量磁存储器件，其中用于写入的磁场对于所有存储元件几乎是均匀的。通过减小当掩模图案彼此接近时在光刻中发生的抗蚀剂图案的变形来实现。磁存储器件是由大量存储器单元构成的MRAM，每个存储单元包括一个TMR元件，一个用于读取（选择）的晶体管，以及读取将TMR元件连接到晶体管用于读取（选择）的插头。这些存储单元被布置成使得TMR元件处于平移对称的图案。对于写入，存储单元通过位线和与正交相交的写入字线连接。 TMR元件的长轴相对于这些线取向倾斜45°，使得TMR元件能够进行触发模式写入。

3. 发明授权

US07005715B2 Magnetic storage device and method of fabricating the same 失效
标题翻译：磁存储装置及其制造方法
公开(公告)号：US07005715B2
公开(公告)日：2006-02-28
申请号：US11112372
申请日：2005-04-22
申请人： Ikuo Yoshihara , Makoto Motoyoshi
发明人： Ikuo Yoshihara , Makoto Motoyoshi
IPC分类号： H01L29/76
CPC分类号： H01L27/228 , B82Y10/00
摘要： Problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, are solved at the same time. In a magnetic storage device (1) having write word lines (11) and bit lines (12) formed so as to cross while keeping a predetermined space therebetween, and provided with a TMR element (13) configured so as to sandwich a tunnel insulating layer (303) with a magnetization fixed layer (302) and a storage layer (304) comprising a ferromagnetic layer, in each of thus-formed intersectional region, and there is provided a semiconductor region (22) in which two read transistors (24, 24), which serve as read transistors, are formed, and which comprises a first region (22a) obliquely crosses a projected region of the write word line (11); a second region (22b) formed in parallel with the bit line (12) so as to be continued from one end of the first region; and a third region (22c) formed in parallel with the bit line (12) and so as to be continued from the other end of the first region (22a).
摘要翻译：同时解决本质上归因于其结构的MRAM的可靠性和串扰问题。在具有写入字线（11）和位线（12）的磁存储装置（1）中，形成为跨越其间保持预定间隔而交叉的位线，并且设置有TMR元件（13），其构造成夹着隧道绝缘具有磁化固定层（302）的层（303）和在这样形成的交叉区域的每一个中包含铁磁层的存储层（304），并且设置有半导体区域（22），其中两个读取晶体管，24），其用作读取晶体管，并且其包括与写入字线（11）的投影区域倾斜交叉的第一区域（22a）; 与所述位线（12）平行地形成为从所述第一区域的一端延续的第二区域（22b）; 以及与所述位线（12）平行形成并且从所述第一区域（22a）的另一端延续的第三区域（22c）。

4. 发明申请

US20050185435A1 Magnetic storage device and method of fabricating the same 失效
标题翻译：磁存储装置及其制造方法
公开(公告)号：US20050185435A1
公开(公告)日：2005-08-25
申请号：US11112372
申请日：2005-04-22
申请人： Ikuo Yoshihara , Makoto Motoyoshi
发明人： Ikuo Yoshihara , Makoto Motoyoshi
IPC分类号： G11C11/14 , G11C11/02 , G11C11/15 , G11C19/08 , H01L21/00 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L27/22 , H01L29/00 , H01L29/76 , H01L31/113 , H01L43/08
CPC分类号： H01L27/228 , B82Y10/00
摘要： Problems in reliability and cross-talk of MRAM, which are intrinsically ascribable to the structure thereof, are solved at the same time. In a magnetic storage device (1) having write word lines (11) and bit lines (12) formed so as to cross while keeping a predetermined space therebetween, and provided with a TMR element (13) configured so as to sandwich a tunnel insulating layer (303) with a magnetization fixed layer (302) and a storage layer (304) comprising a ferromagnetic layer, in each of thus-formed intersectional region, and there is provided a semiconductor region (22) in which two read transistors (24, 24), which serve as read transistors, are formed, and which comprises a first region (22a) obliquely crosses a projected region of the write word line (11); a second region (22b) formed in parallel with the bit line (12) so as to be continued from one end of the first region; and a third region (22c) formed in parallel with the bit line (12) and so as to be continued from the other end of the first region (22a).
摘要翻译：同时解决本质上归因于其结构的MRAM的可靠性和串扰问题。在具有写入字线（11）和位线（12）的磁存储装置（1）中，形成为跨越其间保持预定间隔而交叉的位线，并且设置有TMR元件（13），其构造成夹着隧道绝缘具有磁化固定层（302）的层（303）和在这样形成的交叉区域的每一个中包含铁磁层的存储层（304），并且设置有半导体区域（22），其中两个读取晶体管，24），其用作读取晶体管，并且其包括与写入字线（11）的投影区域倾斜交叉的第一区域（22a）; 与所述位线（12）平行地形成为从所述第一区域的一端延续的第二区域（22b）; 以及与所述位线（12）平行形成并且从所述第一区域（22a）的另一端延续的第三区域（22c）。

5. 发明授权

US4734383A Fabricating semiconductor devices to prevent alloy spiking 失效
标题翻译：制造半导体器件以防止合金尖峰
公开(公告)号：US4734383A
公开(公告)日：1988-03-29
申请号：US800954
申请日：1985-11-22
申请人： Shuji Ikeda , Kouichi Nagasawa , Makoto Motoyoshi , Kiyoshi Nagai , Satoshi Meguro
发明人： Shuji Ikeda , Kouichi Nagasawa , Makoto Motoyoshi , Kiyoshi Nagai , Satoshi Meguro
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/08 , H01L21/425
CPC分类号： H01L21/823814 , H01L29/0847 , H01L27/0928
摘要： After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.
摘要翻译：在P和N沟道MOSFET的P型和N型源极区或漏极区的接触孔已经制成了共同的步骤之后，N型杂质被离子注入至少N型源极或漏极区域通过接触孔。将N型杂质退火，形成比N型源区或漏区更深的N型区。在退火处理期间，N型源极或漏极区域被绝缘膜覆盖。

6. 发明申请

US20100276572A1 SEMICONDUCTOR IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体图像传感器模块及其制造方法
公开(公告)号：US20100276572A1
公开(公告)日：2010-11-04
申请号：US11915958
申请日：2006-06-01
申请人： Shin Iwabuchi , Makoto Motoyoshi
发明人： Shin Iwabuchi , Makoto Motoyoshi
IPC分类号： H01L31/101 , H01L31/18
CPC分类号： H04N5/378 , H01L23/481 , H01L24/16 , H01L25/18 , H01L27/115 , H01L27/14607 , H01L27/14612 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14634 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14643 , H01L27/14689 , H01L27/1469 , H01L29/788 , H01L29/792 , H01L2224/0401 , H01L2224/05552 , H01L2224/05554 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/16145 , H01L2224/16237 , H01L2924/00014 , H01L2924/0002 , H01L2924/13091 , H01L2924/1425 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H04N5/2253 , H04N5/374 , H01L2924/00
摘要： A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.
摘要翻译：一种CMOS型半导体图像传感器模块，其中提高了像素开口率，提高了芯片利用效率，并且还实现了所有像素的同时快门操作，并且提供了制造这种半导体图像传感器模块的方法。半导体图像传感器模块通过堆叠具有图像传感器的第一半导体芯片提供，其中布置有由光电转换元件和晶体管组成的多个像素，以及第二半导体芯片，其具有A / D转换器阵列。优选地，通过堆叠具有存储元件阵列的第三半导体芯片来提供半导体图像传感器模块。此外，半导体图像传感器模块通过堆叠具有图像传感器的第一半导体芯片和具有模拟非易失性存储器阵列的第四半导体芯片来提供。

7. 发明授权

US07271010B2 Nonvolatile magnetic memory device and manufacturing method thereof 失效
标题翻译：非易失磁记忆体装置及其制造方法
公开(公告)号：US07271010B2
公开(公告)日：2007-09-18
申请号：US11237138
申请日：2005-09-28
申请人： Makoto Motoyoshi
发明人： Makoto Motoyoshi
IPC分类号： H01L21/00
CPC分类号： H01L27/228 , B82Y10/00 , H01L21/76802
摘要： An TMR-type MRAM comprising a transistor for selection; a first connecting hole; a first wiring (write-in word line); a second insulating interlayer covering a first insulating interlayer and the first wiring; a TRM device formed on the second insulating interlayer; a second wiring (bit line) formed on a third insulating interlayer; and a second connecting hole formed through the second insulating interlayer and connected to the first connecting hole, in which an end face of an extending portion of the other end of the TRM device is in contact with the second connecting hole.
摘要翻译：一种TMR型MRAM，包括用于选择的晶体管; 第一连接孔; 第一个接线（写入字线）; 覆盖第一绝缘夹层和第一布线的第二绝缘夹层; 形成在所述第二绝缘中间层上的TRM器件; 形成在第三绝缘中间层上的第二布线（位线）; 以及第二连接孔，其形成为穿过所述第二绝缘夹层并连接到所述第一连接孔，所述TRM装置的另一端的延伸部的端面与所述第二连接孔接触。

8. 发明申请

US20070103191A1 Semiconductor-integrated circuit utilizing magnetoresistive effect elements 失效
标题翻译：采用磁阻效应元件的半导体集成电路
公开(公告)号：US20070103191A1
公开(公告)日：2007-05-10
申请号：US11600096
申请日：2006-11-16
申请人： Minoru Sugawara , Makoto Motoyoshi
发明人： Minoru Sugawara , Makoto Motoyoshi
IPC分类号： H03K19/173
CPC分类号： H01L27/228 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/14601 , H01L27/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device able to configure a desired circuit in accordance with a circuit configuration instruction signal given from the outside and able to operate the configured circuit is provided. The semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in the conductive state or the nonconductive state, and a plurality of circuit selection switching elements, wherein said circuit selection switching elements are driven in response to the circuit configuration instruction signal, control signals are output from the circuit selection switching elements, and the desired circuit is configured by combining the circuit elements via said connection elements which become the conductive state or the nonconductive state in accordance with the control signals. As the connection elements, preferably use is made of magnetoresistance effect elements or resistance control elements which become the conductive state or the nonconductive state in accordance with application of a magnetic field. As the circuit elements, use can be made of magnetoresistance effect elements or resistance control elements.
摘要翻译：提供一种能够根据从外部给出的并能够操作配置的电路的电路配置指令信号来配置期望电路的半导体集成电路器件。半导体集成电路器件具有多个电路元件，多个连接元件各自变为导通状态或非导通状态，用于提供用于将连接元件置于导通状态或非导通状态的控制信号的互连，以及多个电路选择开关元件，其中响应于电路配置指令信号驱动所述电路选择开关元件，从电路选择开关元件输出控制信号，并且期望的电路通过经由所述连接元件组合电路元件其根据控制信号变为导通状态或非导通状态。作为连接元件，优选使用根据磁场的施加而成为导通状态或非导通状态的磁阻效应元件或电阻控制元件。作为电路元件，可以使用磁阻效应元件或电阻控制元件。

9. 发明授权

US07109045B2 Method for preparing a ring-formed body, and magnetic memory device and method for manufacturing the same 失效
标题翻译：环形体的制备方法和磁记忆装置及其制造方法
公开(公告)号：US07109045B2
公开(公告)日：2006-09-19
申请号：US10786259
申请日：2004-02-25
申请人： Kojiro Yagami , Makoto Motoyoshi
发明人： Kojiro Yagami , Makoto Motoyoshi
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228 , H01L43/08
摘要： A method of preparing a ring-formed body comprises the steps of: forming, on a substrate, a column in a columnar form which serves as a core of a ring-formed body; depositing, on both the substrate and the column, a ring-formed body forming film for forming the ring-formed body so that the ring-formed body forming film formed on the substrate and that formed on the column are separated from each other; forming a mask film for covering the ring-formed body forming film; and subjecting the mask film and ring-formed body forming film to anisotropic dry etching so that the films remain on a sidewall of the column, forming a ring-formed body comprised of the ring-formed body forming film having the mask film.
摘要翻译：一种制备环成形体的方法包括以下步骤：在基材上形成以圆柱形式形成的作为环形体的芯的柱; 在基板和列两者上沉积用于形成环形体的环形本体形成膜，使得形成在基板上并形成在柱上的环成形体形成膜彼此分离; 形成用于覆盖所述环形体形成膜的掩模膜; 并对掩模膜和环形体形成膜进行各向异性干蚀刻，使得膜保留在柱的侧壁上，形成由具有掩模膜的环形体形成膜构成的环形体。

10. 发明授权

US5700705A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5700705A
公开(公告)日：1997-12-23
申请号：US470452
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元的制造，其中负载MISFET堆叠在半导体衬底上方和驱动MISFET上方。每个负载MISFET的制造包括在同一多晶硅膜内形成源极，漏极和沟道区域，以及由不同层导电膜（例如多晶膜）组成的栅电极，而不是驱动MISFET。具有这种堆叠布置的存储单元的制造有助于其每个负载MISFET的源极（漏极）区域和栅极电极的图案化，以使得彼此之间具有重叠关系，从而增加与每个负载MISFET相关联的有效电容存储单元存储节点。驱动和负载MISFET的栅电极分别由n型或n型和p型多晶硅膜形成，并且在第一和第二p沟道负载MISFET的漏极区之间形成电连接与第一和第二n沟道驱动MISFET的漏极区分别通过分离的多晶硅膜。此外，通过第一和第二驱动MISFET的多晶硅栅电极，在第一和第二负载MISFET的多晶硅栅电极与第二和第一驱动MISFET的漏极区域之间形成电连接此外，SRAM的存储单元分别。

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