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1. 发明申请

US20110211395A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110211395A1
公开(公告)日：2011-09-01
申请号：US13036525
申请日：2011-02-28
申请人： Makoto MIAKASHI , Katsuaki Isobe , Noboru Shibata
发明人： Makoto MIAKASHI , Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3436
摘要： A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.
摘要翻译：一种半导体存储器件，其中可以减少相邻单元之间的干扰并且可以抑制芯片面积的扩大，其包括：存储单元阵列，其中连接到多个字线和多个位线的多个存储器单元被布置在矩阵中形成; 读出放大器中的每一个将连接到每个位线; 控制电路，其控制字线和位线的电压，并将数据编程到存储器单元中或从存储器单元读取数据; 其中所述多个位线至少包括彼此相邻的第一，第二，第三和第四位线，并且所述读出放大器至少包括第一和第二读出放大器，第一和第四选择晶体管是设置在第一和第四位线与第一读出放大器之间，并将第一和第四位线连接到第一读出放大器; 以及设置在第二和第三位线和第二读出放大器之间的第二和第三选择晶体管，并将第二和第三位线连接到第二读出放大器。

2. 发明授权

US08514640B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08514640B2
公开(公告)日：2013-08-20
申请号：US13036525
申请日：2011-02-28
申请人： Makoto Miakashi , Katsuaki Isobe , Noboru Shibata
发明人： Makoto Miakashi , Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3436
摘要： A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and the third bit lines and the second sense amplifier, and connect the second and the third bit lines to the second sense amplifier.
摘要翻译：一种半导体存储器件，其中可以减少相邻单元之间的干扰并且可以抑制芯片面积的扩大，其包括：存储单元阵列，其中连接到多个字线和多个位线的多个存储器单元被布置在矩阵中形成; 读出放大器中的每一个将连接到每个位线; 控制电路，其控制字线和位线的电压，并将数据编程到存储器单元中或从存储器单元读取数据; 其中所述多个位线至少包括彼此相邻的第一，第二，第三和第四位线，并且所述读出放大器至少包括第一和第二读出放大器，第一和第四选择晶体管是设置在第一和第四位线与第一读出放大器之间，并将第一和第四位线连接到第一读出放大器; 以及设置在第二和第三位线和第二读出放大器之间的第二和第三选择晶体管，并将第二和第三位线连接到第二读出放大器。

3. 发明申请

US20110238889A1 SEMICONDUCTOR MEMORY DEVICE FROM WHICH DATA CAN BE READ AT LOW POWER 审中-公开
标题翻译：半导体存储器件，可从低功耗读取数据
公开(公告)号：US20110238889A1
公开(公告)日：2011-09-29
申请号：US12884648
申请日：2010-09-17
申请人： Makoto Miakashi , Noboru Shibata
发明人： Makoto Miakashi , Noboru Shibata
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/26 , G11C16/3436
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列和控制电路。存储单元阵列由以矩阵图案排列的多个存储单元组成。控制电路在第二存储器单元中设置第一标志数据，以便将数据写入存储单元阵列的多个第一存储单元，第二存储单元已经与第一存储器单元同时被选择，在从第一存储器单元读取数据之前，在第二存储单元中设置第一标志数据，并且如果第一标志数据未被设置在第二存储器单元中，则不从第一存储器单元读取数据并输出第一逻辑电平的数据，并且如果第一标志数据被设置在第二存储器单元中，则从第一存储器单元读取数据。

4. 发明申请

US20090141553A1 SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE 有权
标题翻译：具有电荷积累层和控制栅的存储单元提供的半导体存储器件
公开(公告)号：US20090141553A1
公开(公告)日：2009-06-04
申请号：US12365590
申请日：2009-02-04
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

5. 发明授权

US07388790B2 Semiconductor memory device and dynamic latch refresh method thereof 有权
标题翻译：半导体存储器件及其动态锁存刷新方法
公开(公告)号：US07388790B2
公开(公告)日：2008-06-17
申请号：US11510733
申请日：2006-08-28
申请人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
发明人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/70 , G11C29/832 , G11C2211/565 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.
摘要翻译：半导体集成电路器件包括动态锁存器，开关电路，电容器，第一静态锁存器和第一传输门。在动态锁存器的刷新数据中，存储在第一静态锁存器中的数据通过第一传送门移动到第二节点并被保存。动态锁存器的数据被自举。自举数据被传送到第一节点以分配费用，从而设置第一节点的电位。设置电位被写回到动态锁存器来刷新它。第二节点的保存数据通过第一传输门移动到第一节点并写回到第一静态锁存器。

6. 发明授权

US09129688B2 Semiconductor memory device capable of reducing chip size 有权
标题翻译：能够减少芯片尺寸的半导体存储器件
公开(公告)号：US09129688B2
公开(公告)日：2015-09-08
申请号：US13608713
申请日：2012-09-10
申请人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/16 , G11C16/04 , H01L27/115
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

7. 发明授权

US07808821B2 Nonvolatile semiconductor memory including memory cell for storing multilevel data having two or more values 有权
标题翻译：非易失性半导体存储器，包括用于存储具有两个或更多个值的多电平数据的存储单元
公开(公告)号：US07808821B2
公开(公告)日：2010-10-05
申请号：US12204207
申请日：2008-09-04
申请人： Mikio Ogawa , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
发明人： Mikio Ogawa , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.
摘要翻译：写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。

8. 发明授权

US07751243B2 Semiconductor memory device provided with MOS transistor having charge accumulation layer and control gate and data write method of NAND flash memory 失效
标题翻译：具有具有电荷累积层的MOS晶体管和NAND闪存的控制栅极和数据写入方法的半导体存储器件
公开(公告)号：US07751243B2
公开(公告)日：2010-07-06
申请号：US12208798
申请日：2008-09-11
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C8/08 , G11C11/5628 , G11C16/10 , G11C2211/565
摘要： A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second voltages to the bit lines connected to the memory cell transistors in which the “0” data and “1” data is to be programmed respectively, when the selection transistor is turned on, in a write operation. The page buffer is adopted to put the bit line into electrically floating after the first voltage and the second voltage are applied. The row decoder is adopted to apply a third voltage to a semiconductor layer on which the memory cell transistors are formed, and apply a program voltage to the selected word line when the bit line is in the electrically floating.
摘要翻译：半导体存储器件包括存储单元组，选择晶体管，页缓冲器和行解码器。存储单元组包括串联连接的存储单元晶体管。选择晶体管连接到存储单元晶体管。采用页缓冲器将第一和第二电压施加到连接到存储单元晶体管的位线，其中当写选择晶体管导通时，分别对“0”数据和“1”数据进行编程操作。在施加第一电压和第二电压之后，采用页面缓冲器将位线置于电浮置中。采用行解码器将第三电压施加到其上形成有存储单元晶体管的半导体层，并且当位线处于电浮置时将编程电压施加到所选择的字线。

9. 发明申请

US20080043528A1 SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE 有权
标题翻译：具有电荷积累层和控制栅的存储单元提供的半导体存储器件
公开(公告)号：US20080043528A1
公开(公告)日：2008-02-21
申请号：US11770199
申请日：2007-06-28
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

10. 发明申请

US20070247133A1 VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：电压发生电路和包括其的半导体存储器件
公开(公告)号：US20070247133A1
公开(公告)日：2007-10-25
申请号：US11739397
申请日：2007-04-24
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G05F3/04
CPC分类号： G11C7/14 , G11C5/147
摘要： A voltage generation circuit comprises a reference voltage generation circuit; a differential amplifier; an output node; a P-channel MOS transistor; a first resistor series; a second resistor series; a third resistor series; and a selection control circuit. A reference voltage generated by the reference voltage generation circuit is input to a first input terminal of the differential amplifier. The first resistor series is connected between a drain of the P-channel MOS transistor and the output node. The second resistor series is connected between the output node and a second input terminal of the differential amplifier. The third resistor array is connected between the second input terminal of the differential amplifier and a ground. The selection control circuit controls such that a sum of the resistances of the first resistor series and the second resistor series is constant
摘要翻译：电压产生电路包括参考电压产生电路; 差分放大器; 输出节点; P沟道MOS晶体管; 第一个电阻器系列; 第二个电阻器系列; 第三电阻器系列; 和选择控制电路。由参考电压产生电路产生的参考电压被输入到差分放大器的第一输入端。第一个电阻器系列连接在P沟道MOS晶体管的漏极和输出节点之间。第二电阻器系列连接在差分放大器的输出节点和第二输入端子之间。第三电阻阵列连接在差分放大器的第二输入端和地之间。选择控制电路控制使得第一电阻器系列和第二电阻器系列的电阻之和恒定

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