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1. 发明申请

US20070196991A1 SEMICONDUCTOR DEVICE HAVING A STRAIN INDUCING SIDEWALL SPACER AND A METHOD OF MANUFACTURE THEREFOR 审中-公开
标题翻译：具有感应平台间隙的应变的半导体器件及其制造方法
公开(公告)号：US20070196991A1
公开(公告)日：2007-08-23
申请号：US11610908
申请日：2006-12-14
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Mehta , Lahir Adam
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Mehta , Lahir Adam
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure over a substrate, and forming a strain inducing sidewall spacer proximate a sidewall of the gate structure, the strain inducing sidewall configured to introduce strain in a channel region below the gate structure.
摘要翻译：本发明提供一种半导体器件的制造方法以及半导体器件。除了其他步骤之外，该方法可以包括在衬底上形成栅极结构，以及在栅极结构的侧壁附近形成应变诱导侧壁间隔，所述应变诱导侧壁被配置为在栅极结构下方的沟道区域中引入应变。

2. 发明申请

US20090170277A1 IMPLANT DAMAGE OF LAYER FOR EASY REMOVAL AND REDUCED SILICON RECESS 有权
标题翻译：对于易于去除和减少的硅损伤的层的损伤
公开(公告)号：US20090170277A1
公开(公告)日：2009-07-02
申请号：US12345414
申请日：2008-12-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/764 , H01L21/302
CPC分类号： H01L21/76254 , H01L21/3086 , H01L21/31111 , H01L21/32139
摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
摘要翻译：提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

3. 发明授权

US07772094B2 Implant damage of layer for easy removal and reduced silicon recess 有权
标题翻译：植入物损伤层易于去除和减少硅凹陷
公开(公告)号：US07772094B2
公开(公告)日：2010-08-10
申请号：US12345414
申请日：2008-12-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/322
CPC分类号： H01L21/76254 , H01L21/3086 , H01L21/31111 , H01L21/32139
摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.
摘要翻译：提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

4. 发明申请

US20090004805A1 Damage Implantation of a Cap Layer 有权
标题翻译：盖层的损伤植入
公开(公告)号：US20090004805A1
公开(公告)日：2009-01-01
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L23/58
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

5. 发明授权

US08859377B2 Damage implantation of a cap layer 有权
标题翻译：损伤植入帽层
公开(公告)号：US08859377B2
公开(公告)日：2014-10-14
申请号：US11771269
申请日：2007-06-29
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8238 , H01L29/66 , H01L21/3115
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，以及执行源/漏退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

6. 发明申请

US20100252887A1 Damage Implantation of a Cap Layer 审中-公开
标题翻译：盖层的损伤植入
公开(公告)号：US20100252887A1
公开(公告)日：2010-10-07
申请号：US12817829
申请日：2010-06-17
申请人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
发明人： Mahalingam Nandakumar , Wayne Bather , Narendra Singh Mehta
IPC分类号： H01L29/78
CPC分类号： H01L29/7847 , H01L21/31155 , H01L21/8238 , H01L21/823807 , H01L21/823814 , H01L29/6659
摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.
摘要翻译：一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

7. 发明申请

US20060172556A1 Semiconductor device having a high carbon content strain inducing film and a method of manufacture therefor 审中-公开
标题翻译：具有高碳含量应变诱导膜的半导体器件及其制造方法
公开(公告)号：US20060172556A1
公开(公告)日：2006-08-03
申请号：US11344998
申请日：2006-02-01
申请人： Wayne Bather , Narendra Mehta , Troy Yocum
发明人： Wayne Bather , Narendra Mehta , Troy Yocum
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： C23C16/345 , H01L21/0217 , H01L21/02211 , H01L21/02271 , H01L21/3125 , H01L21/3185 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device as well as a semiconductor device. The method, among other steps, may include forming a gate structure (230) over a substrate (210), and forming a strain inducing film (330, 520, 530 or 810) over the substrate (210) and proximate the gate structure (230), the strain inducing film (330, 520, 530 or 810) comprising a bis t-butylaminosilane (BTBAS) silicon nitride layer formed using ratio of bis t-butylaminosilane (BTBAS) to ammonia (NH3) of 1:1 or greater.
摘要翻译：本发明提供一种半导体器件的制造方法以及半导体器件。除了其他步骤之外，该方法可以包括在衬底（210）上形成栅极结构（230），并且在衬底（210）上并且靠近栅极结构（210）处形成应变诱导膜（330,520,530或810） 230），包含使用双叔丁基氨基硅烷（BTBAS）与氨（NH 3）的比率形成的双叔丁基氨基硅烷（BTBAS）氮化硅层的应变诱导膜（330,520,530或810） >）为1：1或更大。

8. 发明申请

US20070015347A1 Strain modulation employing process techniques for CMOS technologies 有权
标题翻译：采用CMOS技术的工艺技术进行应变调制
公开(公告)号：US20070015347A1
公开(公告)日：2007-01-18
申请号：US11183348
申请日：2005-07-18
申请人： Narendra Mehta , Wayne Bather , Ajith Varghese
发明人： Narendra Mehta , Wayne Bather , Ajith Varghese
IPC分类号： C12P21/06
CPC分类号： H01L21/823807 , H01L21/265 , H01L21/823878 , H01L29/7843 , H01L29/7846
摘要： A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.
摘要翻译：一种方法形成包括可修改的应变诱导层的半导体器件。提供半导体本体。识别半导体主体的第一和第二区域。在第一和第二区域内的器件上形成可修改的拉伸应变诱导层。然后形成露出第二区域并覆盖第一区域的掩模。选择材料用于修改植入物，并且将所选择的材料注入第二区域，从而将可修改的拉伸应变诱导层的一部分转化为PMOS区域内的压缩应变诱导层。

9. 发明申请

US20050189660A1 Source drain and extension dopant concentration 审中-公开
标题翻译：源极漏极和延伸掺杂剂浓度
公开(公告)号：US20050189660A1
公开(公告)日：2005-09-01
申请号：US10858644
申请日：2004-06-02
申请人： Haowen Bu , Amitabh Jain , Wayne Bather , Stephanie Butler
发明人： Haowen Bu , Amitabh Jain , Wayne Bather , Stephanie Butler
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76 , H01L21/338
CPC分类号： H01L29/6659 , H01L29/6656 , H01L29/7833
摘要： A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.
摘要翻译：形成半导体器件的方法包括在栅叠层的外表面上形成一个或多个侧壁间隔层。至少部分形成的半导体器件的至少一个区域被掺杂。第一和第二侧壁体形成在栅极堆叠的相对侧上。第一和第二侧壁体的形成包括在栅极堆叠的外表面和侧壁间隔层上形成第一侧壁形成层，将半导体器件暴露于单个晶片反应器中的加热循环，以及形成第二侧壁在第一侧壁形成层的外表面上形成层。第二侧壁形成层的形成发生在基本上最小化部分形成的半导体器件的至少一个区域中的掺杂剂损失和失活的环境中。

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