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    • 1. 发明授权
    • Hardware arithmetic engine for lambda rule computations
    • 用于λ规则计算的硬件算术引擎
    • US07904497B2
    • 2011-03-08
    • US11554704
    • 2006-10-31
    • Irfan NasirTom MathewMagdi A. MohamedJon L. SchindlerWeimin Xiao
    • Irfan NasirTom MathewMagdi A. MohamedJon L. SchindlerWeimin Xiao
    • G06F17/10
    • H03H17/0261
    • A recursive lambda rule engine (114, 302) includes a first multiplier (204) that sequentially multiplies each of series of inputs by a nonlinearity determining parameter and supplies results to a second multiplier (214) that multiplies the output of the first multiplier (204) by a previous output of the engine (114, 302). A three input adder (220, 228) sequentially sums the output of the second multiplier (214), inputs from the series of inputs, and the previous output of the engine (114, 302). A shift register (244) is used to feedback the output of the engine (114, 302) to the three input adder (220, 228) and second multiplier (214). A MUX (234) is used to route an initial value through the shift register (244) for the first cycle of operation.
    • 递归λ规则引擎(114,302)包括第一乘法器(204),该第一乘法器(204)通过非线性确定参数顺序地乘以输入序列中的每一个,并将结果提供给第二乘法器(214),该乘法器将第一乘法器 )通过发动机(114,302)的先前输出。 三输入加法器(220,228)将第二乘法器(214)的输出,一系列输入的输入和发动机(114,302)的先前输出顺序相加。 移位寄存器(244)用于将发动机(114,302)的输出反馈到三输入加法器(220,228)和第二乘法器(214)。 MUX(234)用于通过移位寄存器(244)将初始值路由到第一个操作周期。
    • 2. 发明授权
    • Method and apparatus for nonlinear signal and data aggregation
    • 非线性信号和数据聚合的方法和装置
    • US07870180B2
    • 2011-01-11
    • US11554674
    • 2006-10-31
    • Magdi A. MohamedWeimin Xiao
    • Magdi A. MohamedWeimin Xiao
    • G06F7/38
    • G06N3/063G06N3/0427
    • A method (1500) and apparatus (700, 2300, 2400) for aggregating two or more input signals with a versatile reconfigurable signal aggregator. The aggregator (700, 2300, 2400) is reconfigured by adjusting a control signal λ, and can emulate a range of union type signal aggregators, a range of intersection type signal aggregators, and a continuum of functions between the two, including a signal averager. The versatility of the aggregator (700, 2300, 2400) allows systems in which the aggregator (700, 2300, 2400) is incorporated to be highly adaptable, and thereby fosters improved machine learning.
    • 一种用于通过通用可重构信号聚合器聚合两个或多个输入信号的方法(1500)和装置(700,2300,400)。 通过调整控制信号λ来重新配置聚合器(700,2300,400),并且可以模拟联合类型信号聚合器的范围,交集类型信号聚合器的范围以及两者之间的连续的功能,包括信号平均器 。 聚合器(700,2300,400)的多功能性允许将聚合器(700,2300,400)并入的系统高度适应,从而促进改进的机器学习。
    • 3. 发明授权
    • Configurable infinite logic signal processing network and genetic computing method of designing the same
    • 可配置的无限逻辑信号处理网络和遗传算法的设计方法相同
    • US07761392B2
    • 2010-07-20
    • US11554734
    • 2006-10-31
    • Magdi A. MohamedWeimin XiaoChi Zhou
    • Magdi A. MohamedWeimin XiaoChi Zhou
    • G06N3/00G06N3/02G06F15/18
    • G06N3/126
    • Signal processing networks (700, 800, 1008, 1010, 1012) that include a configurable infinite logic aggregator (100) that can be configured as an infinite logic AND gate and infinite logic OR gate or as other gates along a continuum of function between the two by adjusting control signal magnitudes and a configurable infinite logic signal inverter (500) are provided. A method of designing such networks that includes a genetic programming program (1802) e.g., a gene expression programming program (1600), for designing the network topology, in combination with a numerical optimization (1804), e.g., a hybrid genetic algorithm/differential evolution numerical optimization (1700) for setting control signal values of the network and optionally other numerical parameters is provided.
    • 信号处理网络(700,800,1008,1010,1012),其包括可配置的无限逻辑聚合器(100),其可被配置为无限逻辑与门和无限逻辑“或”门,或者沿着连续的功能的其他门 提供两个通过调节控制信号幅度和可配置的无限逻辑信号反相器(500)。 一种设计这样的网络的方法,其包括遗传编程程序(1802),例如用于设计网络拓扑的基因表达编程程序(1600),结合数字优化(1804),例如混合遗传算法/差分 提供了用于设置网络的控制信号值和可选的其他数值参数的演进数值优化(1700)。
    • 4. 发明申请
    • ARTIFICIAL NEURAL NETWORK WITH ADAPTABLE INFINITE-LOGIC NODES
    • 具有适应性无限逻辑语言的人工神经网络
    • US20080154816A1
    • 2008-06-26
    • US11554724
    • 2006-10-31
    • Weimin XiaoMagdi A. Mohamed
    • Weimin XiaoMagdi A. Mohamed
    • G06F15/18G06N3/02
    • G06N3/02
    • An Artificial Neural Network (110) includes a hidden layer (209) of distance metric computer nodes (210, 214, 218) that evaluate distances of a input vector from metric space centers, an additional layer of adaptable infinite logic aggregators (236, 240, 244) that combine the per-unit distance output values by the distance metric computer nodes (210, 214, 218) using adaptable infinite logic. In certain embodiments the adaptable infinite logic aggregators include veracity signal pre-processors (602, 702) that can be configured to make inferences in a continuum from positive to negative including no inference from each distance and infinite logic connective signal processors (604, 702) that can implement a continuum of functions covering the range of fuzzy logic union operators, fuzzy logic intersection operators, and all linear and nonlinear averaging operators between them. Control parameters (e.g., αi, βi, λA, λD, wi) of the distance metric computer nodes and adaptable infinite logic aggregators can be determined by direct search optimization, using training data.
    • 人造神经网络(110)包括评估来自度量空间中心的输入向量的距离的距离度量计算机节点(210,214,218)的隐藏层(209),附加的适应性无限逻辑聚合器层(236,240) ,244),其使用适应性无限逻辑将每单位距离输出值与所述距离度量计算机节点(210,214,218)组合。 在某些实施例中,适应性无限逻辑聚合器包括真实性信号预处理器(602,702),其可以被配置为在从正到负的连续体中进行推断,包括不包括每个距离的推理和无限逻辑连接信号处理器(604,702) 可以实现覆盖模糊逻辑联合运算符,模糊逻辑交集运算符以及它们之间的所有线性和非线性平均算子的范围的连续函数。 控制参数(例如,α1,λ2,λ1,N 2,N 2, 可以通过使用训练数据的直接搜索优化来确定距离度量计算机节点和适应性无限逻辑聚合器的
    • 7. 发明申请
    • HARWARE ARITHMETIC ENGINE FOR LAMBDA RULE COMPUTATIONS
    • 用于拉姆达法规计算的硬件算术引擎
    • US20080104159A1
    • 2008-05-01
    • US11554704
    • 2006-10-31
    • Irfan NasirTom MathewMagdi A. MohamedJon L. SchindlerWeimin Xiao
    • Irfan NasirTom MathewMagdi A. MohamedJon L. SchindlerWeimin Xiao
    • G06F7/38
    • H03H17/0261
    • A recursive lambda rule engine (114, 302) includes a first multiplier (204) that sequentially multiplies each of series of inputs by a nonlinearity determining parameter and supplies results to a second multiplier (214) that multiplies the output of the first multiplier (204) by a previous output of the engine (114, 302). A three input adder (220, 228) sequentially sums the output of the second multiplier (214), inputs from the series of inputs, and the previous output of the engine (114, 302). A shift register (244) is used to feedback the output of the engine (114, 302) to the three input adder (220, 228) and second multiplier (214). A MUX (234) is used to route an initial value through the shift register (244) for the first cycle of operation.
    • 递归λ规则引擎(114,302)包括第一乘法器(204),该第一乘法器(204)通过非线性确定参数顺序地乘以输入序列中的每一个,并将结果提供给第二乘法器(214),该乘法器将第一乘法器 )通过发动机(114,302)的先前输出。 三输入加法器(220,228)将第二乘法器(214)的输出,一系列输入的输入和发动机(114,302)的先前输出顺序相加。 移位寄存器(244)用于将发动机(114,302)的输出反馈到三输入加法器(220,228)和第二乘法器(214)。 MUX(234)用于通过移位寄存器(244)将初始值路由到第一个操作周期。
    • 8. 发明申请
    • CONFIGURABLE INFINITE LOGIC SIGNAL PROCESSING NETWORK AND GENETIC COMPUTING METHOD OF DESIGNING THE SAME
    • 可配置无限逻辑信号处理网络及其设计的遗传计算方法
    • US20080103995A1
    • 2008-05-01
    • US11554734
    • 2006-10-31
    • Magdi A. MohamedWeimin XiaoChi Zhou
    • Magdi A. MohamedWeimin XiaoChi Zhou
    • G06F3/02G06F15/18
    • G06N3/126
    • Signal processing networks (700, 800, 1008, 1010, 1012) that include a configurable infinite logic aggregator (100) that can be configured as an infinite logic AND gate and infinite logic OR gate or as other gates along a continuum of function between the two by adjusting control signal magnitudes and a configurable infinite logic signal inverter (500) are provided. A method of designing such networks that includes a genetic programming program (1802) e.g., a gene expression programming program (1600), for designing the network topology, in combination with a numerical optimization (1804), e.g., a hybrid genetic algorithm/differential evolution numerical optimization (1700) for setting control signal values of the network and optionally other numerical parameters is provided.
    • 信号处理网络(700,800,1008,1010,1012),其包括可配置的无限逻辑聚合器(100),其可被配置为无限逻辑与门和无限逻辑“或”门,或者沿着连续的功能的其他门 提供两个通过调节控制信号幅度和可配置的无限逻辑信号反相器(500)。 一种设计这样的网络的方法,其包括遗传编程程序(1802),例如用于设计网络拓扑的基因表达编程程序(1600),结合数字优化(1804),例如混合遗传算法/差分 提供了用于设置网络的控制信号值和可选的其他数值参数的演进数值优化(1700)。