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1. 发明申请

US20080104159A1 HARWARE ARITHMETIC ENGINE FOR LAMBDA RULE COMPUTATIONS 失效
标题翻译：用于拉姆达法规计算的硬件算术引擎
公开(公告)号：US20080104159A1
公开(公告)日：2008-05-01
申请号：US11554704
申请日：2006-10-31
申请人： Irfan Nasir , Tom Mathew , Magdi A. Mohamed , Jon L. Schindler , Weimin Xiao
发明人： Irfan Nasir , Tom Mathew , Magdi A. Mohamed , Jon L. Schindler , Weimin Xiao
IPC分类号： G06F7/38
CPC分类号： H03H17/0261
摘要： A recursive lambda rule engine (114, 302) includes a first multiplier (204) that sequentially multiplies each of series of inputs by a nonlinearity determining parameter and supplies results to a second multiplier (214) that multiplies the output of the first multiplier (204) by a previous output of the engine (114, 302). A three input adder (220, 228) sequentially sums the output of the second multiplier (214), inputs from the series of inputs, and the previous output of the engine (114, 302). A shift register (244) is used to feedback the output of the engine (114, 302) to the three input adder (220, 228) and second multiplier (214). A MUX (234) is used to route an initial value through the shift register (244) for the first cycle of operation.
摘要翻译：递归λ规则引擎（114,302）包括第一乘法器（204），该第一乘法器（204）通过非线性确定参数顺序地乘以输入序列中的每一个，并将结果提供给第二乘法器（214），该乘法器将第一乘法器）通过发动机（114,302）的先前输出。三输入加法器（220,228）将第二乘法器（214）的输出，一系列输入的输入和发动机（114,302）的先前输出顺序相加。移位寄存器（244）用于将发动机（114,302）的输出反馈到三输入加法器（220,228）和第二乘法器（214）。 MUX（234）用于通过移位寄存器（244）将初始值路由到第一个操作周期。

2. 发明授权

US07904497B2 Hardware arithmetic engine for lambda rule computations 失效
标题翻译：用于λ规则计算的硬件算术引擎
公开(公告)号：US07904497B2
公开(公告)日：2011-03-08
申请号：US11554704
申请日：2006-10-31
申请人： Irfan Nasir , Tom Mathew , Magdi A. Mohamed , Jon L. Schindler , Weimin Xiao
发明人： Irfan Nasir , Tom Mathew , Magdi A. Mohamed , Jon L. Schindler , Weimin Xiao
IPC分类号： G06F17/10
CPC分类号： H03H17/0261
摘要： A recursive lambda rule engine (114, 302) includes a first multiplier (204) that sequentially multiplies each of series of inputs by a nonlinearity determining parameter and supplies results to a second multiplier (214) that multiplies the output of the first multiplier (204) by a previous output of the engine (114, 302). A three input adder (220, 228) sequentially sums the output of the second multiplier (214), inputs from the series of inputs, and the previous output of the engine (114, 302). A shift register (244) is used to feedback the output of the engine (114, 302) to the three input adder (220, 228) and second multiplier (214). A MUX (234) is used to route an initial value through the shift register (244) for the first cycle of operation.
摘要翻译：递归λ规则引擎（114,302）包括第一乘法器（204），该第一乘法器（204）通过非线性确定参数顺序地乘以输入序列中的每一个，并将结果提供给第二乘法器（214），该乘法器将第一乘法器）通过发动机（114,302）的先前输出。三输入加法器（220,228）将第二乘法器（214）的输出，一系列输入的输入和发动机（114,302）的先前输出顺序相加。移位寄存器（244）用于将发动机（114,302）的输出反馈到三输入加法器（220,228）和第二乘法器（214）。 MUX（234）用于通过移位寄存器（244）将初始值路由到第一个操作周期。

3. 发明申请

US20080101512A1 FAST Q-FILTER 有权
标题翻译：快速过滤器
公开(公告)号：US20080101512A1
公开(公告)日：2008-05-01
申请号：US11554689
申请日：2006-10-31
申请人： Magdi A. Mohamed , Tom Mathew , Irfan Nasir
发明人： Magdi A. Mohamed , Tom Mathew , Irfan Nasir
IPC分类号： H04B1/10
CPC分类号： H03H17/0263 , H03H21/0016
摘要： An nonlinear digital signal processing filter (100, 200, 1100, 1308, 1310, 1312, 1346, 1604) maintains a magnitude ordering for successive windows of signal samples. A set of filter density generator values [f1, f2, f3 . . . fj . . . fndensities] are used according to the ordering in a recursion relation that computes successive values of a set function over the set of filter density generator values. The recursion relation involves an adjustable nonlinearity defining parameter λ. The values are normalized by dividing by a largest of the values, and differences between successive values are taken. An inner product between each window of signal values (used in order according to magnitude) and the adaptive differences is a filtered signal sample.
摘要翻译：非线性数字信号处理滤波器（100,200，1100,1308,1310,1312,1346,1604）维持信号样本的连续窗口的幅度顺序。一组滤波器密度发生器值[f 1，...，f 2，f 3 3]。。。 f＆lt; j＆gt;。。。根据递归关系中的顺序使用f _{，这个递归关系计算过滤器密度发生器值集合上的集合函数的连续值。递归关系涉及可调非线性定义参数λ。通过除以最大的值来对值进行归一化，并且采用连续值之间的差异。信号值（根据大小顺序使用）和自适应差异的每个窗口之间的内积是滤波信号样本。}

4. 发明授权

US07656978B2 Fast Q-filter 有权
标题翻译：快速Q过滤器
公开(公告)号：US07656978B2
公开(公告)日：2010-02-02
申请号：US11554689
申请日：2006-10-31
申请人： Magdi A. Mohamed , Tom Mathew , Irfan Nasir
发明人： Magdi A. Mohamed , Tom Mathew , Irfan Nasir
IPC分类号： H04B1/10
CPC分类号： H03H17/0263 , H03H21/0016
摘要： An nonlinear digital signal processing filter (100, 200, 1100, 1308, 1310, 1312, 1346, 1604) maintains a magnitude ordering for successive windows of signal samples. A set of filter density generator values [f1, f2, f3 . . . fj . . . fndensities] are used according to the ordering in a recursion relation that computes successive values of a set function over the set of filter density generator values. The recursion relation involves an adjustable nonlinearity defining parameter λ. The values are normalized by dividing by a largest of the values, and differences between successive values are taken. An inner product between each window of signal values (used in order according to magnitude) and the adaptive differences is a filtered signal sample.
摘要翻译：非线性数字信号处理滤波器（100,200，1100,1308,1310,1312,1346,1604）维持信号样本的连续窗口的幅度顺序。一组滤波器密度发生器值[f1，f2，f3。。。 fj。。。灵敏度]根据递归关系的顺序使用，该递归关系计算过滤器密度发生器值集合上的集合函数的连续值。递归关系涉及可调非线性定义参数λ。通过除以最大的值来对值进行归一化，并且采用连续值之间的差异。信号值（根据大小顺序使用）和自适应差异的每个窗口之间的内积是滤波信号样本。

5. 发明申请

US20100287273A1 SYSTEM AND METHOD FOR DIRECTING COMMUNICATIONS WITHIN A HETEROGENEOUS NETWORK ENVIRONMENT 审中-公开
标题翻译：在异构网络环境中指挥通信的系统和方法
公开(公告)号：US20100287273A1
公开(公告)日：2010-11-11
申请号：US12435921
申请日：2009-05-05
申请人： Irfan Nasir , Lih-Tyng Hwang , Magdi A. Mohamed , Aroon V. Tungare
发明人： Irfan Nasir , Lih-Tyng Hwang , Magdi A. Mohamed , Aroon V. Tungare
IPC分类号： G06F15/173 , H04B7/26
CPC分类号： H04W48/18 , H04W88/06 , Y02D70/142 , Y02D70/144 , Y02D70/162 , Y02D70/164
摘要： Disclosed is a communications device that monitors the status of its communications links. When more than one communications link is available, an “appropriate” link is selected for use by an application running on the device. The links are continually monitored, and, as circumstances change, the link selection can also change. In some embodiments, a link is “appropriate” when it is available to transfer data and when it satisfies certain “hard” rules set by the application or by a user of the communications device. Some embodiments monitor the behaviour of the communications device and of its user and capture that behaviour in “soft” rules that are applied when selecting an appropriate link and when the hard rules leave the choice open. When multiple links transmit on the same frequency, they may be supported “virtually simultaneously” by time-slicing the actual data transmissions. Unneeded links may be shut down to save battery power.
摘要翻译：公开了一种监视其通信链路的状态的通信设备。当有多个通信链路可用时，选择“适当”链接以供在设备上运行的应用程序使用。链接被不断监视，随着情况的变化，链接选择也可以改变。在一些实施例中，当链路可用于传输数据时以及当它满足由应用或由通信设备的用户设置的某些“硬”规则时，链路是“适当的”。一些实施例监视通信设备及其用户的行为，并且在选择适当链接时应用的“软”规则捕获该行为以及当硬规则离开选择时是否被打开。当多个链路在相同频率上传输时，可以通过对实际的数据传输进行时间分片来“虚拟地同时地”支持它们。可能关闭不需要的链接以节省电池电量。

6. 发明授权

US07446694B1 System for synchronization of multi-sensor data 有权
标题翻译：多传感器数据同步系统
公开(公告)号：US07446694B1
公开(公告)日：2008-11-04
申请号：US11755341
申请日：2007-05-30
申请人： Mohamed I. Ahmed , Faisal Ishtiaq , Magdi A. Mohamed , Irfan Nasir
发明人： Mohamed I. Ahmed , Faisal Ishtiaq , Magdi A. Mohamed , Irfan Nasir
IPC分类号： H03M1/36
CPC分类号： H03M1/1255
摘要： A multi-sensor system includes a first analog sensor sub-system, a second analog sensor sub-system, and a system for synchronizing the outputs of the first and second analog sub-systems. Each analog sensor sub-system includes a sensor that produces an analog output. Each sensor is coupled to analog circuitry that processes the output from the sensor. The system for synchronizing the outputs of the first and second analog sensor sub-systems simultaneously inserts a marker into the outputs of the first and second analog sensors. Then, the outputs of the analog circuitry of the first and second analog sub-systems are synchronized based upon the marker. The marker signal may be produced using a Barker sequence signal generator.
摘要翻译：多传感器系统包括第一模拟传感器子系统，第二模拟传感器子系统和用于同步第一和第二模拟子系统的输出的系统。每个模拟传感器子系统包括产生模拟输出的传感器。每个传感器耦合到处理传感器输出的模拟电路。用于同步第一和第二模拟传感器子系统的输出的系统同时将标记插入到第一和第二模拟传感器的输出中。然后，第一和第二模拟子系统的模拟电路的输出基于标记进行同步。标记信号可以使用巴克序列信号发生器产生。

7. 发明授权

US07406212B2 Method and system for parallel processing of Hough transform computations 有权
标题翻译：霍夫变换计算并行处理方法与系统
公开(公告)号：US07406212B2
公开(公告)日：2008-07-29
申请号：US11143169
申请日：2005-06-02
申请人： Magdi A. Mohamed , Irfan Nasir
发明人： Magdi A. Mohamed , Irfan Nasir
IPC分类号： G06K9/36 , G06F17/14
CPC分类号： G06K9/4633
摘要： In a parallel computation of a Hough transform of an array of input data values, the transform space of the Hough transform is partitioned dynamically or statically into a number of sub-spaces. Each sub-space of the transform is stored in a sub-space of memory locations. Data values from the array of input data values are passed to a plurality of processors, each processor associated dynamically or statically with a sub-space of memory locations. Each processor, acting in parallel with the other processors, updates constituent elements of the Hough transform stored in the associated sub-space memory locations dependent upon the input data value.
摘要翻译：在输入数据值阵列的霍夫变换的并行计算中，将霍夫变换的变换空间动态地或静态分割成多个子空间。变换的每个子空间存储在存储单元的子空间中。来自输入数据值阵列的数据值被传递到多个处理器，每个处理器动态或静态地与存储器位置的子空间相关联。与其他处理器并行起作用的每个处理器根据输入数据值来更新存储在关联的子空间存储单元中的霍夫变换的组成元素。

8. 发明授权

US07725409B2 Gene expression programming based on Hidden Markov Models 有权
标题翻译：基于隐马尔可夫模型的基因表达编程
公开(公告)号：US07725409B2
公开(公告)日：2010-05-25
申请号：US11758083
申请日：2007-06-05
申请人： Chi Zhou , Magdi A. Mohamed , Weimin Xiao
发明人： Chi Zhou , Magdi A. Mohamed , Weimin Xiao
IPC分类号： G06N3/12
CPC分类号： G06N3/126
摘要： Computer programs (600, 700, 800, 900, 1000) and a programmed computer (1100) for automatically generating computer programs (i.e. sequences of instructions) are provided. The computer programs (600, 700, 800, 900, 1000) use Hidden Markov Models (400, 500) to generate sequences of program tokens, e.g., Gene Expression Programming chromosomes (100). Parameters of the Hidden Markov Models (400, 500) are numerically optimized, for example, by Differential Evolution with a goal of increasing the fitness of automatically generated programs.
摘要翻译：提供了用于自动生成计算机程序（即指令序列）的计算机程序（600,700,800,900,1000）和用于自动生成计算机程序的编程计算机（1100）。计算机程序（600,700,800,900,1000）使用隐马尔可夫模型（400,500）来产生程序令牌序列，例如基因表达编程染色体（100）。隐马尔科夫模型（400,500）的参数通过数字优化，例如，通过差分进化，目标是增加自动生成的程序的适应度。

9. 发明申请

US20080247652A1 Q-METRIC BASED SUPPORT VECTOR MACHINE 审中-公开
标题翻译：基于Q-METRIC的支持矢量机
公开(公告)号：US20080247652A1
公开(公告)日：2008-10-09
申请号：US11696505
申请日：2007-04-04
申请人： Magdi A. Mohamed , Weimin Xiao
发明人： Magdi A. Mohamed , Weimin Xiao
IPC分类号： G06K9/62 , G06K9/46 , G06K9/66
CPC分类号： G06K9/6269 , G06K9/6255
摘要： A Support Vector Machine (110) with a Q-Metric kernel function computer (112) is provided. The Support Vector Machine (110) exhibits improved performance for classification and regression. Pattern recognition systems (100,900) that use the Support Vector Machine (110) are also provided. A Differential Evolution method of training a Support Vector Machine is also provided.
摘要翻译：提供了具有Q度量核功能计算机（112）的支持向量机（110）。支持向量机（110）表现出改进的分类和回归性能。还提供了使用支持向量机（110）的模式识别系统（100,900）。还提供了一种训练支持向量机的差分演化方法。

10. 发明申请

US20080103995A1 CONFIGURABLE INFINITE LOGIC SIGNAL PROCESSING NETWORK AND GENETIC COMPUTING METHOD OF DESIGNING THE SAME 失效
标题翻译：可配置无限逻辑信号处理网络及其设计的遗传计算方法
公开(公告)号：US20080103995A1
公开(公告)日：2008-05-01
申请号：US11554734
申请日：2006-10-31
申请人： Magdi A. Mohamed , Weimin Xiao , Chi Zhou
发明人： Magdi A. Mohamed , Weimin Xiao , Chi Zhou
IPC分类号： G06F3/02 , G06F15/18
CPC分类号： G06N3/126
摘要： Signal processing networks (700, 800, 1008, 1010, 1012) that include a configurable infinite logic aggregator (100) that can be configured as an infinite logic AND gate and infinite logic OR gate or as other gates along a continuum of function between the two by adjusting control signal magnitudes and a configurable infinite logic signal inverter (500) are provided. A method of designing such networks that includes a genetic programming program (1802) e.g., a gene expression programming program (1600), for designing the network topology, in combination with a numerical optimization (1804), e.g., a hybrid genetic algorithm/differential evolution numerical optimization (1700) for setting control signal values of the network and optionally other numerical parameters is provided.
摘要翻译：信号处理网络（700,800,1008,1010,1012），其包括可配置的无限逻辑聚合器（100），其可被配置为无限逻辑与门和无限逻辑“或”门，或者沿着连续的功能的其他门提供两个通过调节控制信号幅度和可配置的无限逻辑信号反相器（500）。一种设计这样的网络的方法，其包括遗传编程程序（1802），例如用于设计网络拓扑的基因表达编程程序（1600），结合数字优化（1804），例如混合遗传算法/差分提供了用于设置网络的控制信号值和可选的其他数值参数的演进数值优化（1700）。

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