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1. 发明授权

US06286090B1 Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches 失效
标题翻译：选择性地强制页表提取之间的干扰顺序和相应数据提取的机制
公开(公告)号：US06286090B1
公开(公告)日：2001-09-04
申请号：US09084621
申请日：1998-05-26
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo
IPC分类号： G06F1200
CPC分类号： G06F12/1054 , G06F12/0813
摘要： A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.
摘要翻译：一种技术选择性地将由多处理器系统的处理器发出的存储器参考操作之间的参考间排序施加于与由翻译缓冲器（TB）错过流程程影响的页表项（PTE）相关的页面内的地址。 TB错误流被用于检索包含在PTE中的信息，用于将虚拟地址映射到物理地址，并且随后允许在映射的物理地址处检索数据。响应于存储器引用（读取）操作检索的PTE不会被加载到TB中，直到与该读取操作相关联的提交信号返回到处理器。一旦返回了PTE和相关联的提交信号，处理器将PTE加载到TB中，以便它可以用于针对物理地址的数据的后续读取操作。

2. 发明授权

US6085263A Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor 失效
标题翻译：用于采用提交信号和预取以在高性能I / O处理器中维持参考间排序的方法和装置
公开(公告)号：US6085263A
公开(公告)日：2000-07-04
申请号：US956861
申请日：1997-10-24
申请人： Madhumitra Sharma , Chester Pawlowski , Kourosh Gharachorloo , Stephen R. Van Doren , Simon C. Steely, Jr.
发明人： Madhumitra Sharma , Chester Pawlowski , Kourosh Gharachorloo , Stephen R. Van Doren , Simon C. Steely, Jr.
IPC分类号： G06F12/08 , G06F13/12 , G06F13/14
CPC分类号： G06F12/082 , G06F13/124 , G06F12/0862 , G06F2212/621
摘要： An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.
摘要翻译：改进的I / O处理器（IOP）提供高I / O性能，同时在由共享存储器多处理器系统中的一致性模型指定的I / O设备发出的存储器参考操作之间保持参考间排序。 IOP包括退出控制器，其基于对每个操作的提交信号的接收，在操作之间施加参考间排序，其中用于存储器参考操作的提交信号指示操作的明显完成，而不是实际完成操作。此外，IOP包括耦合到I / O缓存的预取控制器，用于将数据预取到高速缓存中，而没有任何排序限制（或无序）。 IOP的有序退休功能与其预取操作分离，这使得后面的操作能够以任意方式执行，从而提高系统的整体性能。

3. 发明授权

US06209065B1 Mechanism for optimizing generation of commit-signals in a distributed shared-memory system 失效
标题翻译：优化分布式共享内存系统中提交信号生成的机制
公开(公告)号：US06209065B1
公开(公告)日：2001-03-27
申请号：US08957230
申请日：1997-10-24
申请人： Stephen R. Van Doren , Simon C. Steely, Jr. , Kourosh Gharachorloo , Madhumitra Sharma
发明人： Stephen R. Van Doren , Simon C. Steely, Jr. , Kourosh Gharachorloo , Madhumitra Sharma
IPC分类号： G06F1314
CPC分类号： G06F9/542 , G06F9/52
摘要： A mechanism optimizes the generation of a commit-signal by control logic of the multiprocessor system in response to a memory reference operation issued by a processor to a local node of a multiprocessor system having a hierarchical switch for interconnecting a plurality of nodes. The mechanism generally comprises a structure that indicates whether the memory reference operation affects other processors of other nodes of the multiprocessor system. An ordering point of the local node generates an optimized commit-signal when the structure indicates that the memory reference operation does not affect the other processors.
摘要翻译：一种机制响应于处理器向具有用于互连多个节点的分层交换机的多处理器系统的本地节点发出的存储器参考操作来优化多处理器系统的控制逻辑的生成提交信号。该机制通常包括指示存储器参考操作是否影响多处理器系统的其他节点的其他处理器的结构。当结构指示存储器参考操作不影响其他处理器时，本地节点的排序点生成优化的提交信号。

4. 发明授权

US6088771A Mechanism for reducing latency of memory barrier operations on a multiprocessor system 失效
标题翻译：减少多处理器系统上存储器屏障操作延迟的机制
公开(公告)号：US6088771A
公开(公告)日：2000-07-11
申请号：US957501
申请日：1997-10-24
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Kourosh Gharachorloo , Stephen R. Van Doren
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Kourosh Gharachorloo , Stephen R. Van Doren
IPC分类号： G06F9/45 , G06F13/00
CPC分类号： G06F9/3004 , G06F8/458 , G06F9/30087 , G06F9/3834
摘要： A technique reduces the latency of a memory barrier (MB) operation used to impose an inter-reference order between sets of memory reference operations issued by a processor to a multiprocessor system having a shared memory. The technique comprises issuing the MB operation immediately after issuing a first set of memory reference operations (i.e., the pre-MB operations) without waiting for responses to those pre-MB operations. Issuance of the MB operation to the system results in serialization of that operation and generation of a MB Acknowledgment (MB-Ack) command. The MB-Ack is loaded into a probe queue of the issuing processor and, according to the invention, functions to pull-in all previously ordered invalidate and probe commands in that queue. By ensuring that the probes and invalidates are ordered before the MB-Ack is received at the issuing processor, the inventive technique provides the appearance that all pre-MB references have completed.
摘要翻译：一种技术减少了用于在处理器向具有共享存储器的多处理器系统发出的存储器参考操作的集合之间施加参考间顺序的存储器屏障（MB）操作的等待时间。该技术包括在发出第一组存储器参考操作（即，预MB操作）之前立即发出MB操作，而不等待对那些MB前操作的响应。向系统发出MB操作会导致该操作的序列化和生成MB确认（MB-Ack）命令。 MB-Ack被加载到发布处理器的探测队列中，并且根据本发明，该功能用于在该队列中引入所有先前订购的无效和探测命令。通过确保在发布处理器接收到MB-Ack之前对探测和无效进行排序，本发明技术提供了所有pre-MB引用完成的外观。

5. 发明授权

US6055605A Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches 失效
标题翻译：用于在具有共享高速缓存的多处理器系统中使用提交信号来减少参考间排序的等待时间的技术
公开(公告)号：US6055605A
公开(公告)日：2000-04-25
申请号：US957544
申请日：1997-10-24
申请人： Madhumitra Sharma , Simon C. Steely, Jr. , Kourosh Gharachorloo , Stephen R. Van Doren
发明人： Madhumitra Sharma , Simon C. Steely, Jr. , Kourosh Gharachorloo , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F13/00 , G06F12/00
CPC分类号： G06F12/084
摘要： A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.
摘要翻译：一种技术减少了具有分配在共享高速缓存的多个处理器之间的共享存储器的多处理器系统中的存储器参考操作组之间的参考间排序的等待时间。根据该技术，共享高速缓存的每个处理器响应由共享该高速缓存的另一个处理器发出的存储器引用操作而继承由多处理器系统的控制逻辑产生的提交信号。提交信号通过指示对系统的那些实体的存储器参考操作的明显完成来促进多处理器系统的处理器和共享存储器实体之间的串行化。

6. 发明授权

US6108737A Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system 失效
标题翻译：用于减少多处理器系统中参考间排序的等待时间的方法和装置
公开(公告)号：US6108737A
公开(公告)日：2000-08-22
申请号：US957097
申请日：1997-10-24
申请人： Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo , Simon C. Steely, Jr.
发明人： Madhumitra Sharma , Stephen R. Van Doren , Kourosh Gharachorloo , Simon C. Steely, Jr.
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/30087 , G06F12/0828 , G06F9/3004 , G06F9/30047 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A mechanism reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory. The mechanism comprises a commit-signal that is generated by control logic of the multiprocessor system in response to an issued memory reference operation. The commit-signal facilitates inter-reference ordering; moreover, the commit signal indicates the apparent completion of the memory reference operation, rather than actual completion of the operation. The apparent completion of an operation occurs substantially sooner than the actual completion of an operation, thereby improving performance of the multiprocessor system.
摘要翻译：一种机制减少了具有共享存储器的多处理器系统中存储器参考操作的集合之间的参考间排序的等待时间。该机制包括响应于发出的存储器参考操作而由多处理器系统的控制逻辑产生的提交信号。提交信号促进参考间的排序; 此外，提交信号指示存储器参考操作的明显完成，而不是实际完成操作。操作的明显完成大大早于实际完成操作，从而提高了多处理器系统的性能。

7. 发明授权

US06801986B2 Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation 失效
标题翻译：在加载锁定/存储条件原子存储器操作期间，通过延迟所有权所有权投降来实现预防行为
公开(公告)号：US06801986B2
公开(公告)日：2004-10-05
申请号：US09933536
申请日：2001-08-20
申请人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhumitra Sharma
发明人： Simon C. Steely, Jr. , Stephen R. Van Doren , Madhumitra Sharma
IPC分类号： G06F1200
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/3834
摘要： A method, for executing a load locked and a store conditional instruction in a processor, achieves an atomic read-write operation to a memory block. First the load locked instruction is executed to read a memory block, and the processor in response to executing the load locked instruction issues a read modify system command to read the block and to take ownership of the block by the processor, and also sets a lock flag for the address of the memory block, and writes a value of the memory block into a cache of the processor as a cache copy of the memory block. The lock flag, upon receipt of an invalidate message by the processor for the cache copy of the memory block, is reset if any invalidate messages for the memory block are received by the processor. The processor waits for a selected time interval before the processor surrenders ownership of the memory block upon receipt of an ownership request message, if any is received by the processor after execution of the load locked instruction. The processor executes the store conditional instruction, and the processor in response to executing the store conditional instruction tests the lock flag, and if the lock flag is set, writing to the cache copy of the memory block. The processor ends, in the event that the lock flag is reset, the store conditional instruction and does not write to the cache copy of the memory block.
摘要翻译：一种用于在处理器中执行加载锁定和存储条件指令的方法，对存储器块实现原子读写操作。首先执行加载锁定指令以读取存储器块，并且响应于执行加载锁定指令的处理器发出读取修改系统命令来读取块并由处理器获取块的所有权，并且还设置锁定标记存储器块的地址，并将存储器块的值写入处理器的高速缓存作为存储器块的高速缓存副本。如果处理器接收到存储块的任何无效消息，则锁定标志在由处理器接收到存储器块的高速缓存副本的无效消息时被重置。处理器在接收到所有权请求消息之后处理器递交所述存储器块的所有权，等待处理器选定的时间间隔（如果在执行加载锁定指令之后由处理器接收到）。处理器执行存储条件指令，并且处理器响应于执行存储条件指令测试锁定标志，并且如果设置了锁定标志，则写入存储器块的高速缓存副本。处理器在锁定标志被复位的情况下结束，存储条件指令，并且不写入存储器块的高速缓存副本。

8. 发明授权

US06904465B2 Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch 失效
标题翻译：在采用多级节点间交换机的多处理器系统中的低延迟相互参考排序
公开(公告)号：US06904465B2
公开(公告)日：2005-06-07
申请号：US09843228
申请日：2001-04-26
申请人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren
发明人： Simon C. Steely, Jr. , Madhumitra Sharma , Stephen R. Van Doren
IPC分类号： G06F15/173 , H04L12/56 , G06F13/00 , H04L12/50
CPC分类号： H04L49/102 , G06F15/17393 , H04L49/15
摘要： A multiple-processor system in which a commit message is returned to a source processor that requests a memory access operation so as to indicate the apparent completion of the operation includes a multiple-level switch unit linking nodes that contain the processors. The switch unit includes multiple input switches each of which receives messages from multiple nodes, and a set of output switches whose inputs are the outputs of the input switches and whose outputs are the inputs of the nodes. Each switch processes messages in the order in which they are received by the switch and each output switch follows the same rule as the other output switches.
摘要翻译：将提交消息返回给源处理器的多处理器系统，其请求存储器访问操作以指示操作的明显完成包括链接包含处理器的节点的多级交换单元。开关单元包括多个输入开关，每个输入开关从多个节点接收消息，以及一组输出开关，其输入是输入开关的输出，其输出是节点的输入。每个交换机按交换机接收的顺序处理消息，每个输出交换机遵循与其他输出交换机相同的规则。

9. 发明授权

US06961825B2 Cache coherency mechanism using arbitration masks 有权
标题翻译：使用仲裁掩码的缓存一致性机制
公开(公告)号：US06961825B2
公开(公告)日：2005-11-01
申请号：US09768418
申请日：2001-01-24
申请人： Simon C. Steely, Jr. , Stephen Van Doren , Madhumitra Sharma
发明人： Simon C. Steely, Jr. , Stephen Van Doren , Madhumitra Sharma
IPC分类号： G06F12/08 , H04L29/08 , G06F12/00
CPC分类号： H04L67/2804 , G06F12/0824 , G06F12/0826 , H04L67/2852 , H04L69/329
摘要： A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.
摘要翻译：分布式处理系统包括高速缓存一致性机制，其基本上将网络路由信息编码为扇区存在位。该机制将分区存在位组织为一个或多个仲裁掩码，系统交换机直接解码并使用，以通过系统的一个或多个更高级别路由无效消息。系统的较低级别或级别使用本地路由机制（如本地目录）将无效消息引导到保存感兴趣的数据的各个处理器。

10. 发明授权

US06249520B1 High-performance non-blocking switch with multiple channel ordering constraints 失效
标题翻译：具有多通道排序限制的高性能非阻塞开关
公开(公告)号：US06249520B1
公开(公告)日：2001-06-19
申请号：US08957664
申请日：1997-10-24
申请人： Simon C. Steely, Jr. , Stephen R. VanDoren , Madhumitra Sharma , Craig D. Keefer , David W. Davis
发明人： Simon C. Steely, Jr. , Stephen R. VanDoren , Madhumitra Sharma , Craig D. Keefer , David W. Davis
IPC分类号： H04L1250
CPC分类号： G06F13/4022 , G06F12/0826 , G06F15/17393
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

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