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1. 发明申请

US20170285139A1 SIGNAL GENERATING CIRCUIT 审中-公开
公开(公告)号：US20170285139A1
公开(公告)日：2017-10-05
申请号：US15509580
申请日：2014-10-03
申请人： Mitsubishi Electric Corporation
发明人： Kazuhide HIGUCHI , Nobuhiko ANDO , Koji TSUTSUMI , Hiroyuki MIZUTANI , Morishige HIEDA
IPC分类号： G01S7/35 , G01S13/34
CPC分类号： G01S7/35 , G01S7/40 , G01S7/4008 , G01S13/34 , G01S13/343 , G01S13/345 , H03B23/00 , H03L7/093 , H03L7/18 , H03L7/191 , H04B2001/6912
摘要： A signal generating circuit includes a control voltage setting unit (CVSU) configured to set a control voltage for a chirp signal using voltage-frequency characteristics indicating characteristics of an output frequency versus voltage; a VCO configured to alter the frequency of its output signal by the control voltage; a quadrature demodulator configured to perform quadrature demodulation of the output signal of the VCO to generate an inphase signal and a quadrature signal orthogonal to each other; and a frequency detector configured to detect the frequency of the output signal of the VCO on the basis of the inphase signal and quadrature signal. The CVSU corrects the control voltage by using the voltage-frequency characteristics derived from relationships between the control voltage and the frequency of the output signal of the VCO. The VCO generates the chirp signal based on the control voltage corrected by the CVSU.

2. 发明申请

US20180267159A1 SIGNAL GENERATOR 审中-公开
公开(公告)号：US20180267159A1
公开(公告)日：2018-09-20
申请号：US15761337
申请日：2015-10-01
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Osamu WADA , Hiroyuki MIZUTANI , Kenichi TAJIMA , Morishige HIEDA
IPC分类号： G01S13/34 , G01S7/40 , H03L7/089 , H03L7/197 , H03L7/185
CPC分类号： G01S13/34 , G01S7/35 , G01S7/40 , G01S7/4008 , G01S7/4017 , G01S13/343 , G01S13/345 , H03L7/089 , H03L7/185 , H03L7/197 , H03L2207/12
摘要： A signal generator according to the invention includes: a reference signal source configured to output a clock signal; a phase locked loop (PLL) circuit configured to generate a chirp signal as a feedback loop type circuit including a frequency divider using the clock signal; and a linearity-improvement processor configured to detect a frequency of a chirp signal of an M-th period generated by the PLL circuit where M is an integer greater than or equal to 1, and to control a division ratio of the frequency divider such that a difference between a frequency of a chirp signal generated in (M+1)-th and subsequent periods in the PLL circuit and a desired frequency becomes smaller than a difference between the detected frequency and the desired frequency.

3. 发明申请

US20180309179A1 IN-PHASE CORPORATE-FEED CIRCUIT AND ARRAY ANTENNA APPARATUS 审中-公开
公开(公告)号：US20180309179A1
公开(公告)日：2018-10-25
申请号：US15771188
申请日：2016-02-02
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Hiroyuki MIZUTANI , Kenichi TAJIMA , Morishige HIEDA
IPC分类号： H01P1/18 , H01P1/213 , H01P1/36 , H01P5/18 , H01P1/38 , H01Q21/22 , H01Q21/00
摘要： As a layout requirement imposed on an in-phase corporate-feed circuit, there is provided only a layout requirement to equalize the electric length of a transmission line (4) between one of N T-branch units (6) which is m-th when counted from a start point of a path A, and another one of the T-branch units (6) which is (m+1)-th when counted from the start point of the path A, to that of a transmission line (8) between one of N T-branch units (10) which is m-th when counted from an end point of a path B, and another one of the T-branch units (10) which is (m+1)-th when counted from the end point of the path B. Therefore, the in-phase corporate-feed circuit can be formed in a space smaller than that in which its circuit configuration of tournament type is formed, and downsizing of the circuit size can be achieved.

4. 发明申请

US20220014350A1 PHASE-SYNCHRONIZING CIRCUIT 有权
公开(公告)号：US20220014350A1
公开(公告)日：2022-01-13
申请号：US17482685
申请日：2021-09-23
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Kae MORITA , Kenichi TAJIMA , Hideyuki NAKAMIZO , Hiroyuki MIZUTANI , Osamu WADA
IPC分类号： H04L7/02 , H03L7/00
摘要： The phase-synchronizing circuit according to the present disclosure includes: a signal source to output a signal; a signal separator to output part of the signal from the signal source as a transmission signal and receive a reflected signal of the transmission signal; a first phase controller to change a phase of the transmission signal from the signal separator according to a control signal; a signal reflector to pass the transmission signal from the first phase controller as an output signal and output part of the output signal as the reflected signal; and a phase comparator to receive part of the signal from the signal source as a reference signal, compare a phase of the reference signal with a phase of the reflected signal from the signal reflector, and output the control signal corresponding to a phase difference between the reference signal and the reflected signal to the first phase controller.

5. 发明申请

US20190052252A1 PULSE SHIFT CIRCUIT AND FREQUENCY SYNTHESIZER 审中-公开
公开(公告)号：US20190052252A1
公开(公告)日：2019-02-14
申请号：US16077396
申请日：2017-02-20
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Hideyuki NAKAMIZO , Morishige HIEDA , Hiroyuki MIZUTANI , Kenichi TAJIMA
IPC分类号： H03K5/01
CPC分类号： H03K5/01 , H03K2005/00013 , H03K2005/00286 , H03L7/1976 , H03L7/23 , H03M7/3028
摘要： A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. A pulse shift circuit according to the present invention includes: an integrator to integrate, for every clock, the first signal to be inputted; a quantizer to receive the second signal and to output a pulse signal when an integrated value of the integrator becomes equal to or larger than a signal value of the second signal; a delay circuit to delay the pulse signal; a converter disposed before or after the delay circuit to convert a signal value of the pulse signal into the signal value of the second signal; a subtractor to subtract the signal value of the pulse signal converted by the converter, from the signal value of the first signal to be inputted to the integrator; and an input signal control circuit to receive a third signal, to be disposed before the integrator, and to add a signal value corresponding to the third signal to the first signal to be inputted to the integrator or to block the first signal from being inputted to the integrator for clocks corresponding to the third signal.

6. 发明申请

US20180351595A1 MICROWAVE MODULE 审中-公开
公开(公告)号：US20180351595A1
公开(公告)日：2018-12-06
申请号：US15780288
申请日：2016-12-07
申请人： Mitsubishi Electric Corporation
发明人： Yukinobu TARUI , Makoto KIMURA , Isamu RYOKAWA , Akimichi HIROTA , Hiroyuki MIZUTANI
IPC分类号： H04B1/38 , H05K9/00 , H05K1/02 , H01L23/66
摘要： A microwave module includes an RF device and a multilayer resin substrate. The device includes a metal cover covering at least an internal circuit. The substrate includes a first end face on a side of the device, a second end face on a side opposite to the first end face, a signal through-holes surrounding the circuit and connected to the circuit, ground through-holes surrounding the signal through-holes and connected to the cover, a first surface ground provided on the first end face and connected to the cover, an inner layer surface ground connected to ground through-holes, and an RF transmission line surrounded by the ground through-holes, the first surface ground, and the inner layer surface ground, and connected to the signal through-hole.

7. 发明申请

US20220224507A1 PHASE SYNCHRONIZATION CIRCUIT AND IN-PHASE DISTRIBUTION CIRCUIT 有权
公开(公告)号：US20220224507A1
公开(公告)日：2022-07-14
申请号：US17710377
申请日：2022-03-31
申请人： Mitsubishi Electric Corporation
发明人： Hiroyuki MIZUTANI , Sho IKEDA , Kae MORITA
IPC分类号： H04L7/06 , H04L7/10 , H04L7/00
摘要： In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

8. 发明申请

US20210063558A1 RADAR DEVICE 有权
公开(公告)号：US20210063558A1
公开(公告)日：2021-03-04
申请号：US17083903
申请日：2020-10-29
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Kazuhide HIGUCHI , Jun SHIMOKAWATOKO , Hiroyuki MIZUTANI , Kenichi TAJIMA
IPC分类号： G01S13/12 , G01S13/34 , G01S13/40
摘要： The radar device is provided with a distance calculation unit that calculates a distance correspondence value corresponding to the distance to a target from a digital signal converted by a beat signal detection unit, and calculates the distance to the target from the distance correspondence value.

9. 发明申请

US20200186153A1 SIGNAL SOURCE 审中-公开
公开(公告)号：US20200186153A1
公开(公告)日：2020-06-11
申请号：US16793318
申请日：2020-02-18
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： Osamu WADA , Hiroyuki MIZUTANI , Kenichi TAJIMA
IPC分类号： H03L7/087 , H03L7/099
摘要： Conventional signal sources each have a disadvantage that the noise in a control voltage of a VCO increases, thereby deteriorating the phase noise of an output signal of the signal source.A signal source of the present invention includes: a reference signal source for outputting a reference signal; a phase frequency comparator for detecting a phase difference between the reference signal and an oscillation signal and outputting a signal corresponding to the phase difference; a filter for filtering the signal output by the phase frequency comparator; an oscillator for outputting the oscillation signal depending on the signal filtered by the filter; and an S/H circuit for receiving a clock signal for controlling a phase of the oscillation signal by controlling sampling operation and holding operation, sampling at least one of the oscillation signal and the reference signal in synchronization with the clock signal, and outputting at least one of the sampled reference signal and the sampled oscillation signal to the phase frequency comparator, the S/H circuit disposed between the oscillator and the phase frequency comparator or between the reference signal source and the phase frequency comparator.

10. 发明申请

US20170330838A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20170330838A1
公开(公告)日：2017-11-16
申请号：US15525499
申请日：2014-12-09
申请人： Mitsubishi Electric Corporation
发明人： Hiroyuki MIZUTANI , Hidenori ISHIBASHI , Hideharu YOSHIOKA , Kiyoshi ISHIDA
IPC分类号： H01L23/552 , H01L23/31 , H01L23/00 , H01L23/495
CPC分类号： H01L23/552 , H01L21/561 , H01L23/293 , H01L23/3107 , H01L23/4952 , H01L23/49541 , H01L23/49551 , H01L23/49582 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2224/85 , H01L2224/83 , H01L2924/00012
摘要： A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers molded resin and is electrically connected to the second terminal.

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