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1. 发明申请

US20030227060A1 Semiconductor integrated circuit and method for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20030227060A1
公开(公告)日：2003-12-11
申请号：US10445807
申请日：2003-05-28
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Hiroyuki Yamauchi
IPC分类号： H01L029/76 , H01L029/94
CPC分类号： H01L27/11 , G11C11/412 , H01L27/1104 , Y10S257/903
摘要： First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.
摘要翻译：在一个芯片上形成第一到第三逻辑电路和第一至第三静态随机存取存储器（SRAM）。对第一和第三逻辑电路及其SRAM的电源根据需要关闭，同时保持供给第二逻辑电路及其SRAM的电源。第三个SRAM具有最大的存储容量。将第一至第三SRAM单元阵列的平均通道宽度设置为其他电路块的平均通道宽度的一半或更小，并且将以低速工作的第二和第三SRAM单元阵列的沟道杂质浓度设置得更高比通过额外的离子注入高速运行的第一个SRAM单元阵列的SRAM单元阵列。通过这些设置，为第一SRAM单元阵列提供低阈值电压（Vt）的MOS晶体管，而为第二和第三SRAM单元阵列提供高Vt的MOS晶体管用于泄漏减少。

2. 发明申请

US20030096492A1 Method for fabricating semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20030096492A1
公开(公告)日：2003-05-22
申请号：US10288470
申请日：2002-11-06
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Hiroyuki Yamauchi
IPC分类号： H01L021/3205 , H01L021/4763 , H01L021/311
CPC分类号： H01L22/20 , H01L21/28017 , H01L21/76819 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor integrated circuit device of the present invention forms an insulating film on a semiconductor wafer and forms a mask pattern containing a functional element or a wire on the formed insulating film. Dimensions of the mask pattern are changed in accordance with an amount of process variation occurring in the thickness or dielectric constant of the insulating film during the formation of the insulating film.
摘要翻译：本发明的半导体集成电路器件的制造方法在半导体晶片上形成绝缘膜，并在形成的绝缘膜上形成包含功能元件或线的掩模图案。根据在形成绝缘膜期间绝缘膜的厚度或介电常数发生的工艺变化量，改变掩模图案的尺寸。

3. 发明申请

US20020041197A1 Offsetting comparator device and comparator circuit 审中-公开
公开(公告)号：US20020041197A1
公开(公告)日：2002-04-11
申请号：US10006721
申请日：2001-12-10
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Hiroyuki Yamauchi , Yutaka Terada
IPC分类号： H03L005/00
CPC分类号： H03F3/45717
摘要： An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration. Thus, if the characteristic of the sensed current output from the master comparator circuit has changed due to a potential level variation of the differential signal, then the characteristic of the offset current also changes similarly. Thus, the offsetting comparator device can obtain a constant offset voltage even if the potential level of the differential signal has changed.

4. 发明申请

US20030177331A1 Memory system 失效
标题翻译：内存系统
公开(公告)号：US20030177331A1
公开(公告)日：2003-09-18
申请号：US10329164
申请日：2002-12-24
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Hiroyuki Yamauchi
IPC分类号： G06F012/10
CPC分类号： G06F12/0292 , G06F12/08
摘要： A memory system includes a memory including a plurality of memory regions operating based on an identical principle; and an address conversion device for converting a logical address into a physical address based on a correspondence between an address space and the plurality of memory regions. The correspondence is defined based on an inherent condition regarding a performance of the memory.
摘要翻译：存储器系统包括：存储器，其包括基于相同原理操作的多个存储区域; 以及地址转换装置，用于基于地址空间和多个存储区域之间的对应关系将逻辑地址转换成物理地址。对应关系是基于关于存储器性能的固有条件来定义的。

5. 发明申请

US20030043652A1 Programmed value determining circuit, semiconductor integrated circuit device including the same, and method for determining programmed value 失效
标题翻译：编程值确定电路，包括其的半导体集成电路器件以及用于确定编程值的方法
公开(公告)号：US20030043652A1
公开(公告)日：2003-03-06
申请号：US10232785
申请日：2002-08-28
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Hiroyuki Yamauchi
IPC分类号： G11C007/00
CPC分类号： G11C17/143 , G11C17/14 , G11C17/18
摘要： A programmed value determining circuit is provided in which both the area of the programmable element and the leak current are reduced. During the first period after power is turned on, both the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the storage node is disconnected from the power line VDD and the ground line VSS. During the second period after the first period, at least the NMOS transistor Qn1 is turned on, the storage node is connected to the ground line VSS via the program element 10, and the state of the storage node is detected by the detecting portion 11. During the third period after the second period, the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and the state of the storage node is held by the latch portion 12.
摘要翻译：提供了编程值确定电路，其中可编程元件的面积和漏电流均减小。在电源接通之后的第一时段期间，PMOS晶体管Qp1和NMOS晶体管Qn1都截止，并且存储节点与电源线VDD和接地线VSS断开。在第一时段之后的第二周期期间，至少NMOS晶体管Qn1导通，存储节点经由编程元件10连接到接地线VSS，并且由检测部分11检测存储节点的状态。在第二周期之后的第三周期期间，PMOS晶体管Qp1和NMOS晶体管Qn1截止，存储节点的状态由锁存部12保持。

6. 发明申请

US20020105826A1 SRAM device 有权
标题翻译： SRAM器件
公开(公告)号：US20020105826A1
公开(公告)日：2002-08-08
申请号：US10043134
申请日：2002-01-14
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Hiroyuki Yamauchi , Yoshinori Yamagami
IPC分类号： G11C011/00
CPC分类号： G11C11/419 , G11C7/12 , G11C11/412 , H01L27/1104
摘要： An SRAM device of the present invention is an SRAM device, including: a plurality of bit line pairs that are arranged substantially parallel to one another and connected to different memory cells, respectively; selection means for selecting one bit line pair from among the plurality of bit line pairs; and potential holding means for holding a precharge potential of bit lines that are respectively on opposite sides of the one bit line pair with the one bit line pair being selected, wherein an interval between two adjacent bit line pairs is smaller than an interval between two bit lines of the same bit line pair.
摘要翻译：本发明的SRAM器件是一种SRAM器件，包括：多个位线对，分别基本上彼此平行地布置并连接到不同的存储器单元; 选择装置，用于从所述多个位线对中选择一个位线对; 以及电位保持装置，用于保持分别位于与所选择的一个位线对的一个位线对的相对侧上的位线的预充电电位，其中两个相邻位线对之间的间隔小于两位之间的间隔相同位线对的线。

7. 发明申请

US20020097826A1 Clock recovery circuit 有权
标题翻译：时钟恢复电路
公开(公告)号：US20020097826A1
公开(公告)日：2002-07-25
申请号：US10038613
申请日：2002-01-08
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Toru Iwata , Hiroyuki Yamauchi , Takefumi Yoshikawa
IPC分类号： H03D003/24
CPC分类号： H04L25/45 , H03L7/0807 , H03L7/081 , H03L7/087 , H03L7/0891 , H04L7/033
摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.
摘要翻译：驱动器和接收器提供基于具有常规位模式的串行数据的数据信号，诸如时钟，其包括在调整周期期间彼此交替的1和0，并且基于具有任意的串行数据在调整周期后的转移期间的位模式。占空因数控制器调节驱动器或接收器的数据转换特性，使得从接收器提供的数据信号的占空比在调整周期中等于50％，并且具有被调整的数据转换特性。时钟恢复单元恢复与在传送时段中从接收器提供的数据信号同步的时钟，并且基于来自数据信号的经调整的转换特性。

8. 发明申请

US20040109344A1 Semiconductor memory device 失效
公开(公告)号：US20040109344A1
公开(公告)日：2004-06-10
申请号：US10623691
申请日：2003-07-22
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Hiroyuki Yamauchi
IPC分类号： G11C011/00
CPC分类号： G11C7/12
摘要： In a semiconductor memory device, a precharge potential for non-selected bit lines among a plurality of bit lines, supplied by a HPR voltage source, is set at a value (for example, null Vccnull0.4 V) lower than the power supply voltage Vcc (low voltage in the range of 0.5 V to 1.2 V; for example, 0.8 V) determining the high-level side potential of data stored in a memory cell. A potential for non-selected word lines among a plurality of word lines, supplied by a NWL voltage source, is set at a predetermined negative potential (for example, nullnull Vccnullnull0.2 V). The total of the precharge potential (0.4 V) of non-selected bit lines and the absolute value of the negative potential (null0.2 V) of non-selected word lines is set at a value less than the power supply voltage Vcc (0.8 V). By these settings, gate leakage current and GIDL current can be effectively limited to a small value while realizing effective limitation of OFF leakage current in a plurality of memory cells.

9. 发明申请

US20030088849A1 Semiconductor integrated circuit device and method for designing the same 失效
标题翻译：半导体集成电路器件及其设计方法
公开(公告)号：US20030088849A1
公开(公告)日：2003-05-08
申请号：US10281300
申请日：2002-10-28
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Hiroyuki Yamauchi
IPC分类号： G06F017/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A method for designing a semiconductor integrated circuit device, the method has the steps of producing, for a plurality of placement regions on each of which a design pattern is to be placed, first layout data having a first expected value based on a first layout design rule, producing, if a difference between the first expected data and an expected finished size after fabrication of the first layout data falls within an error tolerance for a standard value, first OPC data by correcting the first layout data, producing, if the plurality of placement regions include an out-of-tolerance region for which the first OPC data falling within the error tolerance cannot be produced, second layout data having a second expected value for the out-of-tolerance region based on a second layout design rule, producing second OPC data by correcting the second layout data such that an expected finished size after fabrication of the second layout data falls within the error tolerance for the standard value, and producing mask data by using the first OPC data and the second OPC data.
摘要翻译：一种用于设计半导体集成电路器件的方法，所述方法具有以下步骤：对于要放置设计图案的多个放置区域，产生基于第一布局设计具有第一预期值的第一布局数据规则，如果第一布局数据的制造之后的第一预期数据和预期成品尺寸之间的差异落在对于标准值的误差容差内，则通过校正第一布局数据来产生第一OPC数据，如果多个放置区域包括不能产生落在误差公差内的第一OPC数据的第二布局数据，其中第二布局数据具有基于第二布局设计规则的超出公差区域的第二预期值，产生通过校正第二布局数据使得第二布局数据的制造之后的预期成品尺寸落在标准值的误差容差内的第二OPC数据 ue，并通过使用第一OPC数据和第二OPC数据产生掩模数据。

10. 发明申请

US20030067819A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20030067819A1
公开(公告)日：2003-04-10
申请号：US10263914
申请日：2002-10-03
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Katsuji Satomi , Hiroyuki Yamauchi
IPC分类号： G11C007/00
CPC分类号： H01L27/1104
摘要： A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.
摘要翻译：半导体存储器件具有SRAM存储单元，其包括：第一反相器，包括第一nMOS晶体管和第一pMOS晶体管; 包括第二nMOS晶体管和第二pMOS晶体管的第二反相器; 第三个nMOS晶体管; 以及第四nMOS晶体管，其中分别形成所述第一和第三nMOS晶体管的第一扩散区域和形成所述第二和第四nMOS晶体管的第二扩散区域被布置成线形，而没有任何弯曲部分，并且所述第一扩散区域的驱动能力并且第二nMOS晶体管高于第三和第四nMOS晶体管的晶体管。

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