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1. 发明申请

US20040268291A1 Method and device for checking lithography data 有权
标题翻译：用于检查光刻数据的方法和装置
公开(公告)号：US20040268291A1
公开(公告)日：2004-12-30
申请号：US10609153
申请日：2003-06-24
申请人： Micron Technology, Inc.
发明人： Husayn Alvarez-Gomariz , John R.C. Futrell
IPC分类号： G06F017/50 , H01L021/66
CPC分类号： G03F1/36 , Y10S715/964
摘要： Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features that occur as a result of photolithographic interference. The additional feature information is obtained through use of simulation methods with reduced processing time or solving a system of equations. This allows a user to quickly find information about additional feature printing before the features are printed, and before the reticle is made.

2. 发明申请

US20040268290A1 REMOVAL OF RELATIVELY UNIMPORTANT SHAPES FROM A SET OF SHAPES 有权
标题翻译：从一组形状中删除相对不可比拟的形状
公开(公告)号：US20040268290A1
公开(公告)日：2004-12-30
申请号：US10604063
申请日：2003-06-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Joseph B. Allen , Timothy G. Dunham , Valarmathi C. Shanmugam
IPC分类号： G06F017/50 , G06F019/00 , G21K005/00
CPC分类号： G06F17/5068 , G03F1/68
摘要： A method for reducing a number of shapes, and a computer readable program code adapted to perform said method. The method forms first and second shape patterns. The second shape pattern includes the first shape pattern and error shapes. The error shapes are extracted from the second shape pattern. At least one environment shape corresponding to each error shape is derived from a subset of the error shapes. For example, each error shape in the subset may be expanded to form a corresponding expanded shape, and at least one environment shape corresponding to each expanded shape may be formed by removing all portions of the expanded shape common to the second shape pattern. The environment shape reflects a local geometric environment of its corresponding error shape. A subset of the environment shapes are deleted such that only unique environment shapes satisfying a selection criterion remain.
摘要翻译：一种用于减少形状的方法，以及适于执行所述方法的计算机可读程序代码。该方法形成第一和第二形状图案。第二形状图案包括第一形状图案和错误形状。从第二形状图案提取错误形状。从错误形状的子集中导出与每个错误形状对应的至少一个环境形状。例如，子集中的每个错误形状可以被扩展以形成对应的扩展形状，并且可以通过去除与第二形状图案相同的扩展形状的所有部分来形成与每个扩展形状对应的至少一个环境形状。环境形状反映了其相应错误形状的局部几何环境。环境形状的一个子集被删除，使得仅保持满足选择标准的独特环境形状。

3. 发明申请

US20040268288A1 CODING OF FPGA AND STANDARD CELL LOGIC IN A TILING STRUCTURE 失效
标题翻译： FPGA和标准单元逻辑在倾斜结构中的编码
公开(公告)号：US20040268288A1
公开(公告)日：2004-12-30
申请号：US10604071
申请日：2003-06-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stanislav Peter Bajuk , Jack Robert Smith , Sebastian Theodore Ventrone
IPC分类号： G06F017/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnectnulls type. The language extensions allow different signal interconnect types, such as those used with field programmable gate arrays (FPGA) and standard cells, to be stored in a same file array hierarchy. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). The transition from one RTL type to another is performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.

4. 发明申请

US20040268274A1 Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs 有权
标题翻译：将重新定义的正常形式应用于流水线设计的抽象RTL描述的形式等价性验证
公开(公告)号：US20040268274A1
公开(公告)日：2004-12-30
申请号：US10608423
申请日：2003-06-30
申请人： Intel Corporation
发明人： Zurab Khasidashvili , John Moondanos , Ziyad Hanna
IPC分类号： G06F017/50
CPC分类号： G06F17/504
摘要： A method for facilitating the sequential verification of loop-free circuits by reducing the sequential verification problem to combinational verification, by constructing and comparing Timed Binary Decision. Diagrams (TBDDs) and Timed Binary Expression Diagrams (TBEDs). The TBEDs can be compared by using both BDDs and SAT solvers.

5. 发明申请

US20040268272A1 Method and apparatus for manufacturing multiple circuit patterns using a multiple project mask 失效
标题翻译：使用多个工程掩模制造多个电路图案的方法和装置
公开(公告)号：US20040268272A1
公开(公告)日：2004-12-30
申请号：US10610002
申请日：2003-06-30
发明人： Reginald C. Farrow , Warren K. Waskiewicz
IPC分类号： G06F017/50
CPC分类号： G03F1/50 , G03F1/00
摘要： A method and apparatus are disclosed for fabricating a substrate having a plurality of circuit patterns. The substrate is exposed to a primary mask having a plurality of the desired circuit patterns, surrounded by one or more exclusion regions, and a secondary mask having a pattern corresponding to the exclusion regions that satisfies at least one design rule for a subsequent process. The primary and secondary masks are exposed on the substrate in any order before the resist patterns are developed. The pattern on the secondary mask may comprise, for example, an array of fill patterns. The pattern on the secondary mask may satisfy design rules for more than one process level so that a single secondary mask can be utilized for multiple process levels. In addition, the substrate only needs to be exposed to the secondary mask for process levels where the exclusion regions violate a design rule.

6. 发明申请

US20040268271A1 High data rate differential signal line design for uniform characteristic impedance for high performance integrated circuit packages 有权
标题翻译：高数据速率差分信号线设计，用于高性能集成电路封装的均匀特性阻抗
公开(公告)号：US20040268271A1
公开(公告)日：2004-12-30
申请号：US10602734
申请日：2003-06-25
发明人： Amit P. Agrawal
IPC分类号： G06F017/50
CPC分类号： H05K1/025 , H01L23/49838 , H01L23/66 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2924/00014 , H01L2924/15173 , H01L2924/15174 , H01L2924/15311 , H01L2924/1903 , H01L2924/3011 , H01P5/02 , H05K1/181 , H05K2201/09236 , H05K2201/09727 , H05K2201/10674 , H05K2201/10734 , H01L2224/0401
摘要： Provided is an apparatus that includes an integrated circuit (IC) mounted on a chip carrier. The IC has one or more differential pair circuits coupled thereto and the chip carrier has a signal escaping portion and a remaining portion. The apparatus also includes differential signal lines coupled to the differential pair circuits, the differential signal lines (i) extending through the chip carrier and (ii) having first and second segments. The first segment extends through the escaping portion and the second segment extends through the remaining portion. The first and second segments have respective first and second widths.
摘要翻译：提供了一种包括安装在芯片载体上的集成电路（IC）的装置。 IC具有耦合到其上的一个或多个差分对电路，并且芯片载体具有信号逸出部分和剩余部分。该装置还包括耦合到差分对电路的差分信号线，延伸穿过芯片载体的差动信号线（i）和（ii）具有第一和第二段。第一段延伸穿过逸出部分，第二段延伸穿过剩余部分。第一和第二段具有相应的第一和第二宽度。

7. 发明申请

US20040267514A1 METHODOLOGY FOR FIXING Qcrit AT DESIGN TIMING IMPACT 失效
标题翻译：在设计时间影响下固定Qcrit的方法
公开(公告)号：US20040267514A1
公开(公告)日：2004-12-30
申请号：US10604179
申请日：2003-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kerry Bernstein , Philip G. Emma , Leendert M. Huisman , Paul D. Kartschoke , Norman J. Rohrer
IPC分类号： G06F009/45 , G06F017/50
CPC分类号： G06F17/5022
摘要： A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.

8. 发明申请

US20040267513A1 Automatic creation of a design for a high or medium voltage power transmission network 审中-公开
标题翻译：自动创建高压或中压输电网络的设计
公开(公告)号：US20040267513A1
公开(公告)日：2004-12-30
申请号：US10640634
申请日：2003-08-14
申请人： ABB Technology AG
发明人： Dirk Westermann , Antonio Carvalho , Paula Rios , Marta Lacorte , Mohamed Rahmani , Peter Bosshart
IPC分类号： G06F017/50
CPC分类号： G06F17/50 , G06F2217/78 , H02J3/00 , H02J2003/007 , Y02E60/76 , Y04S40/22
摘要： A design for a high or medium voltage power transmission network is created automatically. The network comprises a plurality of subsystems that are classifiable as switchgear, transformers, transmission lines, or network controllers such as compensators, where each subsystem comprises a plurality of components, where components exist in different embodiments having different technical and economical characteristics, and where the design comprises, for each subsystem, a selection of components such that the subsystem satisfies given technical and financial criteria. The following steps are performed: a) inputting a set of solution alternatives characterizing the network, b) determining for each solution alternative at least one set of solution constraints for each subsystem, c) automatically determining, for each subsystem and for each of the at least one sets of solution constraints, a cost-optimal subsystem that satisfies the solution constraints, and determining subsystem performance data that characterizes the cost-optimal subsystem, d) combining, for each solution alternative, the performance data of the corresponding cost-optimal subsystems and determining performance data of the solution alternative.

9. 发明申请

US20040261052A1 Method for programming a mask-programmable logic device and device so programmed 有权
标题翻译：用于编程掩码可编程逻辑器件和如此编程的器件的方法
公开(公告)号：US20040261052A1
公开(公告)日：2004-12-23
申请号：US10875256
申请日：2004-06-23
申请人： ALTERA CORPORATION, a corporation of Delaware
发明人： Steven Perry , Gregor Nixon , Larry Kong , Alasdair Scott , Andrew Hall , Lingli Wang , Chris Dettmar , Jonathan Park , Richard Price
IPC分类号： G06F017/50 , H03K019/00
CPC分类号： G06F17/5045 , G06F17/5054
摘要： A user logic design for a mask-programmable logic device (nullMPLDnull) may be designed on a comparable or compatible user-programmable logic device (nullUPLDnull) and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLDnulli.e., differences between the devicesnullare taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.
摘要翻译：可以在可比较或兼容的用户可编程逻辑器件（“UPLD”）上设计用于掩模可编程逻辑器件（“MPLD”）的用户逻辑设计并迁移到MPLD，或者可以直接设计在MPLD上。如果设计是在UPLD上设计的，则会考虑目标MPLD的约束，即设备之间的差异，以便迁移将成功。如果设计直接在MPLD上设计，则如果用户指示设计将迁移到UPLD进行测试，则会考虑可比较的兼容UPLD的约束。这意味着当逻辑设计旨在在UPLD和MPLD之间进行迁移时，只能使用特征交集。为了便于迁移，可以创建成对的设备之间的固定映射。

10. 发明申请

US20040261050A1 Designing and testing the interconnection of addressable devices of integrated circuits 失效
标题翻译：设计和测试集成电路可寻址器件的互连
公开(公告)号：US20040261050A1
公开(公告)日：2004-12-23
申请号：US10465186
申请日：2003-06-19
申请人： LSI LOGIC CORPORATION
发明人： Robert Neal Carlton Broberg III , Troy Evan Faber , Gary Scott Delp , Paul Gary Reuland , Daniel James Murray
IPC分类号： G06F017/50
CPC分类号： G06F17/5045
摘要： A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters. The register address generation tool may be used with a suite of generation tools to achieve the rapid design and realization of a new semiconductor product.
摘要翻译：在半导体产品的设计中使用寄存器地址生成工具。对于可在总线上寻址的寄存器和/或存储器，寄存器地址生成工具创建互连RTL，头文件，静态时序分析约束文件和验证测试用例。该工具还在设计中保持半导体产品设计中所产生的内容和可用资源之间的一致性。如果没有使用任何寄存器和/或存储器，则寄存器地址生成工具可以进一步产生将将这些未使用的资源转换成诸如控制寄存器，状态寄存器等的性能增强特征的RTL。寄存器地址生成工具读取具有应用集的设计数据库，以确定什么硬件和什么晶体管结构可用。它还接收总线规范和地址参数作为输入。寄存器地址生成工具可以与一套生成工具一起使用，以实现新的半导体产品的快速设计和实现。

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