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1. 发明申请

US20010032328A1 Semiconductor integrated circuit realizing electrical interface 有权
标题翻译：半导体集成电路实现电接口
公开(公告)号：US20010032328A1
公开(公告)日：2001-10-18
申请号：US09828936
申请日：2001-04-10
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Yutaka Terada , Hironori Akamatsu , Satoshi Takahashi , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F011/00
CPC分类号： H04L12/40052 , H04L12/40032
摘要： A semiconductor integrated circuit includes receiver, potential sensor and output fixing circuit. The receiver receives a differential signal that has been transmitted through a twisted pair of signal lines, and outputs a signal in accordance with the differential signal. The potential sensor senses a variation in in-phase potential of the differential signal transmitted through the twisted pair. And the output fixing circuit fixes an output of the receiver at a certain value if the variation sensed by the potential sensor is equal to or greater than a predetermined level. In this configuration, once the variation in the in-phase potential of the differential signal has reached the predetermined level, the output of the receiver is fixed at the certain value. Accordingly, even if the receiver operates erroneously due to the in-phase potential variation, the erroneous output of the receiver is not supplied to the next stage like a digital section.
摘要翻译：半导体集成电路包括接收器，电位传感器和输出固定电路。接收机接收通过双绞信号线发送的差分信号，并根据差分信号输出信号。电位传感器检测通过双绞线传输的差分信号的同相电位变化。如果由电位传感器感测到的变化量等于或大于预定水平，则输出固定电路将接收器的输出固定在一定值。在该配置中，一旦差分信号的同相电位的变化已经达到预定电平，则接收器的输出被固定在该特定值。因此，即使接收器由于同相电位变化而错误地操作，接收机的错误输出也不像数字部分那样被提供给下一个级。

2. 发明申请

US20010007418A1 Common mode bias generator 有权
公开(公告)号：US20010007418A1
公开(公告)日：2001-07-12
申请号：US09734191
申请日：2000-12-12
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Yoshihide Komatsu , Hironori Akamatsu , Takashi Hirata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G05F001/40
CPC分类号： G05F3/205
摘要： An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.

3. 发明申请

US20020041197A1 Offsetting comparator device and comparator circuit 审中-公开
公开(公告)号：US20020041197A1
公开(公告)日：2002-04-11
申请号：US10006721
申请日：2001-12-10
申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人： Hiroyuki Yamauchi , Yutaka Terada
IPC分类号： H03L005/00
CPC分类号： H03F3/45717
摘要： An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration. Thus, if the characteristic of the sensed current output from the master comparator circuit has changed due to a potential level variation of the differential signal, then the characteristic of the offset current also changes similarly. Thus, the offsetting comparator device can obtain a constant offset voltage even if the potential level of the differential signal has changed.

4. 发明申请

US20030076731A1 Multiport semiconductor memory 失效
标题翻译：多端口半导体存储器
公开(公告)号：US20030076731A1
公开(公告)日：2003-04-24
申请号：US10271829
申请日：2002-10-15
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Yutaka Terada
IPC分类号： G11C008/16
CPC分类号： G11C8/16
摘要： A semiconductor memory having ports, each of which conducts exclusively a writing or reading operation, by which the access operation can be speeded up when cells at the same row address are accessed simultaneously through two ports, is provided. A current-carrying capability of a write access transistor making up a memory cell is lowered relative to a current-carrying capability of a read access transistor within a range capable of finishing the writing operation.
摘要翻译：一种具有端口的半导体存储器，每个端口都进行专门的写入或读取操作，当通过两个端口同时访问相同行地址的单元时，可以加速存取操作。构成存储单元的写入存取晶体管的载流能力相对于能够完成写入操作的范围内的读取存取晶体管的载流能力降低。

5. 发明申请

US20020047729A1 Voltage level detection circuit and voltage level detection method 失效
公开(公告)号：US20020047729A1
公开(公告)日：2002-04-25
申请号：US09978676
申请日：2001-10-18
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Takashi Hirata , Hironori Akamatsu , Satoshi Takahashi , Yoshihide Komatsu , Yutaka Terada , Hirokazu Sugimoto
IPC分类号： H03D001/00
CPC分类号： H03M1/0626 , H03M1/0872 , H03M1/145 , H03M1/34 , H03M1/36
摘要： In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

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