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1. 发明授权

US06632707B1 Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权
标题翻译：使用CVD有机BARC形成互连结构以减轻中毒的方法
公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译：在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。

2. 发明授权

US06514860B1 Integration of organic fill for dual damascene process 有权
标题翻译：有机填料的整合用于双镶嵌工艺
公开(公告)号：US06514860B1
公开(公告)日：2003-02-04
申请号：US09892750
申请日：2001-06-28
申请人： Lynne A. Okada , Fei Wang , James K. Kai
发明人： Lynne A. Okada , Fei Wang , James K. Kai
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.
摘要翻译：制造半导体器件的方法包括：在第一层上形成第二阻挡层，在第二阻挡层上形成第一介电层，在第一介电层上形成第二电介质层，蚀刻第一和第二电介质层，形成第通过第一电介质层和第二电介质层开口，在蚀刻第二介电层之前将有机填充材料沉积在开口中并去除一部分有机填充材料以形成沟槽。然后可以完全去除有机填充材料，并且蚀刻第二阻挡层以暴露第一层。然后用导电材料填充沟槽和通孔以形成特征。

3. 发明授权

US06767827B1 Method for forming dual inlaid structures for IC interconnections 有权
标题翻译：用于形成用于IC互连的双镶嵌结构的方法
公开(公告)号：US06767827B1
公开(公告)日：2004-07-27
申请号：US10459328
申请日：2003-06-11
申请人： Lynne A. Okada , Fei Wang , James Kai
发明人： Lynne A. Okada , Fei Wang , James Kai
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L2221/1063
摘要： A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer thereover. The method further comprises patterning the cap, dielectric layers and middle stop layer a via opening down to the etch stop layer that is associated with the opening therein. A trench opening is formed down through the cap and second dielectric layer and stopping on the middle stop layer. The trench/via opening is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The first dielectric layer, middle stop layer, second dielectric layer and cap layer are then deposited over both regions and two via openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via formation. A trench pattern is then defined in the second dielectric layer and the etch stop layers are then removed in the openings and a conductive material is formed therein.
摘要翻译：公开了一种形成用于IC的双镶嵌互连结构的方法。该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在其上形成第一介电层，中间停止层，第二介电层和盖层。该方法还包括将盖，电介质层和中间停止层的图形图案化，通孔向下通向与其中的开口相关联的蚀刻停止层。通过盖和第二介电层向下形成沟槽开口，并在中间停止层上停止。然后用导电材料（例如金属）填充沟槽/通孔开口。该方法还可以包括在蚀刻停止层的开口内形成阻挡层。根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率比第一个地区。然后在两个区域上沉积第一介电层，中间阻挡层，第二介电层和盖层，并且在该区域中分别形成两个通孔。第一和第二蚀刻停止层在通孔形成期间保护下面的衬底不经历穿透。然后在第二电介质层中限定沟槽图案，然后在开口中去除蚀刻停止层，并在其中形成导电材料。

4. 发明授权

US06372631B1 Method of making a via filled dual damascene structure without middle stop layer 有权
标题翻译：制造通孔填充双镶嵌结构而不具有中间停止层的方法
公开(公告)号：US06372631B1
公开(公告)日：2002-04-16
申请号：US09778061
申请日：2001-02-07
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which a barrier diffusion layer/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the barrier diffusion layer/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the first dielectric layer to form a second dielectric layer over the via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中阻挡扩散层/蚀刻停止层沉积在导电层上。将无机低k电介质材料沉积在阻挡扩散层/蚀刻停止层上以形成第一介电层。蚀刻第一介电层以在第一介电层中形成通孔。有机低k介电材料沉积在通孔内和第一介电层上方，以在通孔和第一介电层上形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的一部分直接在通孔的上方。重新打开的通孔和沟槽填充有导电材料。

5. 发明授权

US06756300B1 Method for forming dual damascene interconnect structure 有权
标题翻译：双镶嵌互连结构的形成方法
公开(公告)号：US06756300B1
公开(公告)日：2004-06-29
申请号：US10324259
申请日：2002-12-18
申请人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
发明人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.
摘要翻译：为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

6. 发明授权

US06656830B1 Dual damascene with silicon carbide middle etch stop layer/ARC 有权
标题翻译：双面镶嵌碳化硅中间蚀刻停止层/ ARC
公开(公告)号：US06656830B1
公开(公告)日：2003-12-02
申请号：US09777695
申请日：2001-02-07
申请人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
发明人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.
摘要翻译：通过采用碳化硅中间蚀刻停止层/ ARC，提高了镶嵌加工中沟槽形成的尺寸精度以及因此的金属线宽度。实施例包括使用具有约-0.10至约-0.60的消光系数（k）的碳化硅中蚀刻停止层/ ARC的第一沟槽最后双镶嵌技术。

7. 发明授权

US06603206B2 Slot via filled dual damascene interconnect structure without middle etch stop layer 有权
标题翻译：通过填充的双镶嵌互连结构的槽，没有中间蚀刻停止层
公开(公告)号：US06603206B2
公开(公告)日：2003-08-05
申请号：US10105509
申请日：2002-03-26
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L23522
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031 , Y10S977/827
摘要： An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中底部抗反射涂层/蚀刻停止层沉积在导电层上。无机低k介电材料沉积在BARC /蚀刻停止层上以形成第一介电层。蚀刻第一介电层以在第一介电层中形成槽通孔。有机低k电介质材料通过第一电介质层和第一介电层上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽沿与槽通孔的长度垂直的方向延伸。沟槽的整个宽度直接在通孔上方。重新打开的通孔和沟槽填充有导电材料。

8. 发明授权

US06521524B1 Via filled dual damascene structure with middle stop layer and method for making the same 有权
标题翻译：通过填充中间停止层的双镶嵌结构和制作相同的方法
公开(公告)号：US06521524B1
公开(公告)日：2003-02-18
申请号：US09778070
申请日：2001-02-07
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the etch stop layer to form a second dielectric layer over the via and the etch stop layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成通孔。有机低k介电材料沉积在通孔内和蚀刻停止层上方，以在通孔和蚀刻停止层上方形成第二电介质层。再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的一部分直接在通孔的上方。重新打开的通孔和沟槽填充有导电材料。

9. 发明授权

US06309955B1 Method for using a CVD organic barc as a hard mask during via etch 有权
标题翻译：在通孔蚀刻期间使用CVD有机棒材作为硬掩模的方法
公开(公告)号：US06309955B1
公开(公告)日：2001-10-30
申请号：US09784065
申请日：2001-02-16
申请人： Ramkumar Subramanian , Fei Wang , Todd P. Lukanc , Lynne A. Okada
发明人： Ramkumar Subramanian , Fei Wang , Todd P. Lukanc , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming a via of a metal interconnect structure in a semiconductor device employs a CVD organic BARC between a low k dielectric material and a via photoresist mask. The CVD organic BARC is deposited over the low k dielectric film and protects the film during formation and patterning of the via photoresist mask. Furthermore, the presence of the BARC permits the photoresist mask to be thinner than that used in conventional techniques thereby improving lithography resolution.
摘要翻译：在半导体器件中形成金属互连结构的通孔的方法在低k电介质材料和通孔光致抗蚀剂掩模之间采用CVD有机BARC。 CVD有机BARC沉积在低k电介质膜上，并在通孔光致抗蚀剂掩模的形成和图案化期间保护膜。此外，BARC的存在允许光致抗蚀剂掩模比常规技术中使用的光刻胶掩模更薄，从而提高光刻分辨率。

10. 发明授权

US07279410B1 Method for forming inlaid structures for IC interconnections 有权
标题翻译：用于形成IC互连的镶嵌结构的方法
公开(公告)号：US07279410B1
公开(公告)日：2007-10-09
申请号：US10379757
申请日：2003-03-05
申请人： Lynne A. Okada , Fei Wang , James Kai
发明人： Lynne A. Okada , Fei Wang , James Kai
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/311
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76829
摘要： A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via or trench formation. The etch stop layers are then removed in the openings and a conductive material is formed therein.
摘要翻译：一种用于形成用于IC的镶嵌互连结构的方法。该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在蚀刻停止层上形成介电层和覆盖层，形成光致抗蚀剂图案，以及蚀刻帽和电介质以形成开口然后用导电材料（例如金属）填充。该方法还可以包括在蚀刻停止层的开口内形成阻挡层。根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率比第一个地区。然后将介电层和盖层沉积在两个区域上，并且分别在区域中形成两个通孔或沟槽开口。第一和第二蚀刻停止层在通孔或沟槽形成期间保护下面的衬底不经历穿透。然后在开口中去除蚀刻停止层，并在其中形成导电材料。

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