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1. 发明申请

US20130145216A1 SYSTEMS AND METHODS FOR HARDWARE-ASSISTED TYPE CHECKING 有权
标题翻译：硬件辅助类型检查的系统和方法
公开(公告)号：US20130145216A1
公开(公告)日：2013-06-06
申请号：US13594607
申请日：2012-08-24
申请人： Susan J. Eggers , Luis Ceze , Emily Fortuna , Owen Anderson
发明人： Susan J. Eggers , Luis Ceze , Emily Fortuna , Owen Anderson
IPC分类号： G06F11/36
CPC分类号： G06F11/3668 , G06F8/437 , G06F11/0712 , G06F11/0772
摘要： Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.
摘要翻译：提供了为动态类型检查提供硬件支持的设备和方法。在一些实施例中，处理器包括类型检查寄存器和支持一个或多个被检查的加载指令。在一些实施例中，正常加载指令由具有检查的加载指令的编译器替代。在一些实施例中，为了执行检查的负载，错误处理程序指令位置被存储在类型检查寄存器中，并且类型标签操作数与存储在加载的存储单元中的类型标签进行比较。如果比较成功，执行可以正常进行。如果比较失败，则可以将执行转移到错误处理程序指令。在一些实施例中，执行类型预测以确定检查的加载指令是否可能失败。

2. 发明授权

US09336125B2 Systems and methods for hardware-assisted type checking 有权
标题翻译：硬件辅助型检查的系统和方法
公开(公告)号：US09336125B2
公开(公告)日：2016-05-10
申请号：US13594607
申请日：2012-08-24
申请人： Susan J. Eggers , Luis Ceze , Emily Fortuna , Owen Anderson
发明人： Susan J. Eggers , Luis Ceze , Emily Fortuna , Owen Anderson
IPC分类号： G06F11/00 , G06F11/36 , G06F11/07 , G06F9/45
CPC分类号： G06F11/3668 , G06F8/437 , G06F11/0712 , G06F11/0772
摘要： Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.
摘要翻译：提供了为动态类型检查提供硬件支持的设备和方法。在一些实施例中，处理器包括类型检查寄存器和支持一个或多个被检查的加载指令。在一些实施例中，正常加载指令由具有检查的加载指令的编译器替代。在一些实施例中，为了执行检查的负载，错误处理程序指令位置被存储在类型检查寄存器中，并且类型标签操作数与存储在加载的存储单元中的类型标签进行比较。如果比较成功，执行可以正常进行。如果比较失败，则可以将执行转移到错误处理程序指令。在一些实施例中，执行类型预测以确定检查的加载指令是否可能失败。

3. 发明授权

US08612955B2 Wavescalar architecture having a wave order memory 失效
标题翻译：波浪式建筑具有波浪记忆
公开(公告)号：US08612955B2
公开(公告)日：2013-12-17
申请号：US12017480
申请日：2008-01-22
申请人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
发明人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
IPC分类号： G06F9/45
CPC分类号： G06F9/5033 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3851 , G06F9/4494 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/526 , G06F15/8023 , G06F2209/5017 , G06F2209/521
摘要： A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
摘要翻译：数据流指令集架构和执行模型，被称为WaveScalar，其设计用于可扩展的低复杂度/高性能处理器，同时通过称为波次序存储器的机制有效地提供传统的存储器语义。波形存储器使得以任何语言编写的“现实世界”程序都可以在WaveScalar架构上运行，也可以执行任何无序执行单元。因为它是软件控制的，所以可以禁用波形顺序的内存来获得更大的并行性。 Wavescalar还包括一个软件控制的标签管理系统。

4. 发明授权

US07657882B2 Wavescalar architecture having a wave order memory 失效
标题翻译：波浪式建筑具有波浪记忆
公开(公告)号：US07657882B2
公开(公告)日：2010-02-02
申请号：US11041396
申请日：2005-01-21
申请人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
发明人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
IPC分类号： G06F9/45
CPC分类号： G06F9/5033 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3851 , G06F9/4494 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/526 , G06F15/8023 , G06F2209/5017 , G06F2209/521
摘要： A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
摘要翻译：数据流指令集架构和执行模型，被称为WaveScalar，其设计用于可扩展的低复杂度/高性能处理器，同时通过称为波次序存储器的机制有效地提供传统的存储器语义。波形存储器使得以任何语言编写的“现实世界”程序都可以在WaveScalar架构上运行，也可以执行任何无序执行单元。因为它是软件控制的，所以可以禁用波形顺序的内存来获得更大的并行性。 Wavescalar还包括一个软件控制的标签管理系统。

5. 发明授权

US06314511B1 Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers 失效
公开(公告)号：US06314511B1
公开(公告)日：2001-11-06
申请号：US09054100
申请日：1998-04-02
申请人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
发明人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
IPC分类号： G06F938
摘要： A system and a method is described for freeing renaming registers that have been allocated to architectural registers prior to another instruction redefining the architectural register. Renaming registers are used by a processor to dynamically execute instructions out-of-order. The present invention may be employed by any single or multi-threaded processor that executes instructions out-of-order. A mechanism is described for freeing renaming registers that consists of a set of instructions, used by a compiler, to indicate to the processor when it can free the physical (renaming) register that is allocated to a particular architectural register. This mechanism permits the renaming register to be reassigned or reallocated to store another value as soon as the renaming register is no longer needed for allocation to the architectural register. There are at least three ways to enable the processor with an instruction that identifies the renaming register to be freed from allocation: (1) a user may explicitly provide the instruction to the processor that refers to a particular renaming register; (2) an operating system may provide the instruction when a thread is idle that refers to a set of registers associated with the thread; and (3) a compiler may include the instruction with the plurality of instructions presented to the processor. There are at least five embodiments of the instruction provided to the processor for freeing renaming registers allocated to architectural registers: (1) Free Register Bit; (2) Free Register; (3) Free Mask; (4) Free Opcode; and (5) Free Opcode/Mask. The Free Register Bit instruction provides the largest speedup for an out-of-order processor and the Free Register instruction provides the smallest speedup.

6. 发明申请

US20080133882A1 WAVESCALAR ARCHITECTURE HAVING A WAVE ORDER MEMORY 失效
标题翻译：具有波形存储器的波形建筑
公开(公告)号：US20080133882A1
公开(公告)日：2008-06-05
申请号：US12017480
申请日：2008-01-22
申请人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
发明人： Mark H. Oskin , Steven J. Swanson , Susan J. Eggers
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/5033 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3851 , G06F9/4494 , G06F9/5016 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/526 , G06F15/8023 , G06F2209/5017 , G06F2209/521
摘要： A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
摘要翻译：数据流指令集架构和执行模型，被称为WaveScalar，其设计用于可扩展的低复杂度/高性能处理器，同时通过称为波次序存储器的机制有效地提供传统的存储器语义。波形存储器使得以任何语言编写的“现实世界”程序都可以在WaveScalar架构上运行，也可以执行任何无序执行单元。因为它是软件控制的，所以可以禁用波形顺序的内存来获得更大的并行性。 Wavescalar还包括一个软件控制的标签管理系统。

7. 发明授权

US06427234B1 System and method for performing selective dynamic compilation using run-time information 失效
标题翻译：使用运行时信息执行选择性动态编译的系统和方法
公开(公告)号：US06427234B1
公开(公告)日：2002-07-30
申请号：US09330359
申请日：1999-06-11
申请人： Craig Chambers , Susan J. Eggers , Brian K. Grant , Markus Mock , Matthai Philipose
发明人： Craig Chambers , Susan J. Eggers , Brian K. Grant , Markus Mock , Matthai Philipose
IPC分类号： G06F945
CPC分类号： G06F9/45516
摘要： Selective dynamic compilation of source code is performed using run-time information. A system is disclosed that implements a declarative, annotation based dynamic compilation of the source code, employing a partial evaluation, binding-time analysis (BTA), and including program-point-specific polyvariant division and specialization and dynamic versions of traditional global and peephole optimizations. The system allows programmers to declaratively specify policies that govern the aggressiveness of specialization and caching, providing fine control over the dynamic compilation process. The policies include directions for controlling specialization at promotion points and merge points, and further define caching policies, and speculative-specialization policies. The system also enables programmers to specialize programs across arbitrary edges, both at traditional locations, such as procedure boundaries, but also within procedures. Programmers are enabled to conditionally specialize programs based on evaluation of arbitrary compile-time and run-time conditions.
摘要翻译：使用运行时信息执行源代码的选择性动态编译。公开了一种系统，其实现基于声明的注释的源代码的动态编译，采用部分评估，绑定时间分析（BTA），并且包括程序点特定的多变量分割以及传统全局和窥视孔的专业化和动态版本优化。该系统允许程序员声明性地指定管理专业化和缓存的侵略性的策略，从而对动态编译过程提供精确的控制。这些政策包括在促销点和合并点控制专业化的指导，进一步界定缓存政策和投机专业化政策。该系统还使程序员能够在传统的位置（如过程边界），也在程序内的任意边缘专门化程序。程序员可以根据对任意编译时和运行时条件的评估有条件地专门化程序。

8. 发明授权

US6092175A Shared register storage mechanisms for multithreaded computer systems with out-of-order execution 失效
标题翻译：具有无序执行的多线程计算机系统的共享寄存器存储机制
公开(公告)号：US6092175A
公开(公告)日：2000-07-18
申请号：US53903
申请日：1998-04-02
申请人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
发明人： Henry M. Levy , Susan J. Eggers , Jack Lo , Dean M. Tullsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46
CPC分类号： G06F9/30123 , G06F9/30076 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/462
摘要： A method and organization for implementing the registers required in a computer system supporting multithreading and dynamic out-of-order execution. Multithreaded computer systems are those in which the processor supports multiple contexts (threads), and either rapid context switching from thread to thread or scheduling of instructions from different threads within a single cycle. An important component of processors for such systems is the register file; the processor needs a large register file or resource to provide the registers used for the threads. One form of the invention maintains a set of private architecturally specified registers, and a set of private renaming register for each different thread. In the other three embodiments, sharing of renaming registers between different threads is permitted, to enable a reduction in the total number of registers required. One of these three embodiments enables any of the architecturally specified registers that are private to a thread but are not in use, to be employed as renaming registers. Another of the embodiments treats all registers as sharable and enables any register from the register file or resource to be used as a renaming register for any thread.
摘要翻译：一种用于实现支持多线程和动态无序执行的计算机系统中所需的寄存器的方法和组织。多线程计算机系统是处理器支持多个上下文（线程），以及从单线程到线程的快速上下文切换或来自单个周期内不同线程的指令调度的系统。这种系统的处理器的一个重要组成部分是寄存器文件; 处理器需要一个大的寄存器文件或资源来提供用于线程的寄存器。本发明的一种形式维护一组私有结构上指定的寄存器，以及一组用于每个不同线程的私有重命名寄存器。在其他三个实施例中，允许在不同线程之间共享重命名寄存器，以便能够减少所需的寄存器总数。这三个实施例中的一个使得任何对线程是私有的但不被使用的架构地指定的寄存器被用作重命名寄存器。另一个实施例将所有寄存器视为可共享的，并且使来自寄存器文件或资源的任何寄存器能够用作任何线程的重命名寄存器。

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