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1. 发明授权

US07005387B2 Method for preventing an increase in contact hole width during contact formation 失效
标题翻译：防止接触形成时接触孔宽度增大的方法
公开(公告)号：US07005387B2
公开(公告)日：2006-02-28
申请号：US10705631
申请日：2003-11-08
申请人： Dawn Hopper , Hiroyuki Kinoshita , Christy Woo
发明人： Dawn Hopper , Hiroyuki Kinoshita , Christy Woo
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76814 , H01L21/76865
摘要： According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.
摘要翻译：根据一个示例性实施例，用于在位于半导体管芯中的硅化物层上形成接触的方法包括在接触孔的侧壁和位于接触孔的底部的自然氧化物层上沉积阻挡层的步骤，其中侧壁由电介质层中的接触孔限定。可以优化将阻挡层沉积在接触孔的侧壁和自然氧化物层上的步骤，使得阻挡层在接触孔的顶部具有比接触孔底部的厚度更大的厚度。根据该示例性实施例，该方法还包括去除位于接触孔底部的阻挡层和自然氧化物层的一部分以露出硅化物层的步骤。

2. 发明申请

US20050101148A1 Method for preventing an increase in contact hole width during contact formation 失效
标题翻译：防止接触形成时接触孔宽度增大的方法
公开(公告)号：US20050101148A1
公开(公告)日：2005-05-12
申请号：US10705631
申请日：2003-11-08
申请人： Dawn Hopper , Hiroyuki Kinoshita , Christy Woo
发明人： Dawn Hopper , Hiroyuki Kinoshita , Christy Woo
IPC分类号： H01L21/768 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76814 , H01L21/76865
摘要： According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.
摘要翻译：根据一个示例性实施例，用于在位于半导体管芯中的硅化物层上形成接触的方法包括在接触孔的侧壁和位于接触孔的底部的自然氧化物层上沉积阻挡层的步骤，其中侧壁由电介质层中的接触孔限定。可以优化将阻挡层沉积在接触孔的侧壁和自然氧化物层上的步骤，使得阻挡层在接触孔的顶部具有比接触孔底部的厚度更大的厚度。根据该示例性实施例，该方法还包括去除位于接触孔底部的阻挡层和自然氧化物层的一部分以露出硅化物层的步骤。

3. 发明授权

US07572727B1 Semiconductor formation method that utilizes multiple etch stop layers 有权
标题翻译：利用多个蚀刻停止层的半导体形成方法
公开(公告)号：US07572727B1
公开(公告)日：2009-08-11
申请号：US10934828
申请日：2004-09-02
申请人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
发明人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
摘要翻译：本发明是一种半导体接触形成系统和方法。接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。导电材料（例如，钨）沉积在接触区域中。

4. 发明授权

US06969654B1 Flash NVROM devices with UV charge immunity 有权
标题翻译：具有UV电荷免疫功能的闪存NVROM器件
公开(公告)号：US06969654B1
公开(公告)日：2005-11-29
申请号：US09727714
申请日：2000-11-28
申请人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
发明人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L23/552 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28273 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.
摘要翻译：一种在制造期间防止闪存NVROM单元的紫外线充电的方法和由此形成的装置。在器件制造期间，在阻挡层上沉积UV阻挡层。 UV阻挡层基本上阻止UV进入栅极区域，以便防止电子迁移率足以使电池不可编程或不可擦除。在NVROM处理期间减少的电子迁移导致器件的产量和可靠性的提高。

5. 发明授权

US07361587B1 Semiconductor contact and nitride spacer formation system and method 有权
标题翻译：半导体接触和氮化物间隔物的形成系统及方法
公开(公告)号：US07361587B1
公开(公告)日：2008-04-22
申请号：US10934923
申请日：2004-09-02
申请人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
发明人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829 , H01L21/76831 , Y10S438/97
摘要： The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region width are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
摘要翻译：本发明是形成接触绝缘区域的半导体接触形成系统和方法，该接触绝缘区域包括有助于形成接触的多个蚀刻停止子层。该契约形成过程提供相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。在一个实施例中，多次蚀刻停止触点形成工艺，其中沉积包括多个蚀刻停止层的多重蚀刻停止绝缘层。通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除靠近金属层，并且较小的部分被移除到靠近基板的位置。不同的接触区域宽度通过执行由多个蚀刻停止绝缘层中的多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现。导电材料（例如，钨）沉积在接触区域中。

6. 发明授权

US06867063B1 Organic spin-on anti-reflective coating over inorganic anti-reflective coating 有权
标题翻译：无机抗反射涂层上的有机旋涂抗反射涂层
公开(公告)号：US06867063B1
公开(公告)日：2005-03-15
申请号：US10262221
申请日：2002-09-30
申请人： Kouros Ghandehari , Dawn Hopper , Wenmei Li , Angela T. Hui
发明人： Kouros Ghandehari , Dawn Hopper , Wenmei Li , Angela T. Hui
IPC分类号： G03F7/09 , H01L21/027 , H01L21/02
CPC分类号： G03F7/091 , H01L21/0276
摘要： A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating is organic and may be deposited through a spin-on process. The organic anti-reflective coating may be deposited with more exacting optical properties and better control of the layer thickness than conventional bottom anti-reflective coatings applied via chemical vapor deposition processes. The combination of the two layers of anti-reflective materials, the materials having differing optical properties, demonstrates superior control of reflections from underlying materials compared with conventional art methods. More particularly, an organic anti-reflective coating in conjunction with an inorganic anti-reflective coating may cancel reflections across a wide range of thicknesses in an underlying dielectric layer. The superior anti-reflective structure of embodiments of the present invention allow patterning of semiconductor structures at smaller critical dimensions with greater accuracy, rendering competitive advantages in device speed, density and cost.
摘要翻译：一种制造半导体的方法。常规的底部抗反射涂层施加在反射表面上，例如层间电介质。在第一抗反射涂层上沉积第二抗反射涂层。第二种抗反射涂层是有机的，可通过旋涂工艺沉积。与通过化学气相沉积工艺施加的常规底部抗反射涂层相比，有机抗反射涂层可以沉积更加严格的光学性能和更好的层厚度控制。与传统技术方法相比，两层抗反射材料（具有不同光学性质的材料）的组合表现出对来自下层材料的反射的优异控制。更具体地，结合无机抗反射涂层的有机抗反射涂层可以消除底层电介质层中宽范围的厚度的反射。本发明的实施例的优异的抗反射结构允许以较小的临界尺寸更精确地图案化半导体结构，从而在装置速度，密度和成本方面具有竞争优势。

7. 发明授权

US06410458B1 Method and system for eliminating voids in a semiconductor device 有权
标题翻译：用于消除半导体器件中的空隙的方法和系统
公开(公告)号：US06410458B1
公开(公告)日：2002-06-25
申请号：US09494755
申请日：2000-01-31
申请人： Lu You , Dawn Hopper , John Jianshi Wang
发明人： Lu You , Dawn Hopper , John Jianshi Wang
IPC分类号： H01L2348
CPC分类号： H01L21/76835 , H01L21/76837 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a method and system for eliminating voids in a semiconductor device. The method comprises the steps of forming metal lines over a semiconductor substrate, forming a first oxide layer utilizing a high density plasma deposition technique, forming a second oxide layer utilizing a carbon free resin and forming a topside dielectric layer. Through the use of a method in accordance with the present invention, the voids that are created in the dielectric films during conventional semiconductor processing methodology are eliminated. The use of a high density plasma deposition technique provides a more directional deposition that can get between metal lines that are separated by smaller gaps. The dielectric films are thereby strengthened, which increases the reliability of the semiconductor device. Furthermore, by utilizing hydrogen silsesquiloxane instead of a conventional spin-on glass, there is no concern regarding carbon contamination since hydrogen silsesquiloxane doesn't contain carbon atoms.
摘要翻译：本发明是用于消除半导体器件中的空隙的方法和系统。该方法包括以下步骤：在半导体衬底上形成金属线，利用高密度等离子体沉积技术形成第一氧化物层，利用无碳树脂形成第二氧化物层并形成顶层电介质层。通过使用根据本发明的方法，消除了在常规半导体处理方法中在电介质膜中产生的空隙。使用高密度等离子体沉积技术提供了更多的定向沉积，其可以在由较小间隙分离的金属线之间获得。因此，介电膜被加强，这增加了半导体器件的可靠性。此外，通过使用氢硅氧烷代替常规旋涂玻璃，由于氢硅氧烷不含碳原子，因此不关心碳污染。

8. 发明授权

US06317642B1 Apparatus and methods for uniform scan dispensing of spin-on materials 有权
标题翻译：用于均匀扫描分配旋涂材料的装置和方法
公开(公告)号：US06317642B1
公开(公告)日：2001-11-13
申请号：US09191438
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
发明人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
IPC分类号： G06F1900
CPC分类号： H01L21/6715 , B05D1/005
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

9. 发明授权

US06225240B1 Rapid acceleration methods for global planarization of spin-on films 有权
标题翻译：用于旋涂膜全局平面化的快速加速方法
公开(公告)号：US06225240B1
公开(公告)日：2001-05-01
申请号：US09191101
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Richard J. Huang
发明人： Lu You , Dawn Hopper , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , B05D1/005 , H01L21/02282 , H01L21/31051 , H01L21/312 , H01L21/3124 , H01L21/3127
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of desposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液在晶片上的排列方式。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

10. 发明授权

US6093973A Hard mask for metal patterning 有权
标题翻译：金属图案的硬掩模
公开(公告)号：US6093973A
公开(公告)日：2000-07-25
申请号：US163601
申请日：1998-09-30
申请人： Minh Van Ngo , Bhanwar Singh , Dawn Hopper , Carmen Morales
发明人： Minh Van Ngo , Bhanwar Singh , Dawn Hopper , Carmen Morales
IPC分类号： G03F7/09 , G03F7/11 , H01L23/544
CPC分类号： G03F7/091 , G03F7/11 , Y10S257/915
摘要： An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen free oxide layer on the anti-reflective coating, such as a silicon oxide derived from tertaethyl orthosilicate by plasma enhanced chemical vapor deposition.
摘要翻译：在深紫外光致抗蚀剂和抗反射涂层之间形成氧化物硬掩模以防止与光致抗蚀剂的相互作用，从而防止图案化导电层的临界尺寸的降低。实施方案包括在抗反射涂层上沉积基本上无氮的氧化物层，例如通过等离子体增强化学气相沉积衍生自原硅酸三乙酯的氧化硅。

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